Dual Rail Memory Power Segmentation for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory technologies face challenges in reducing power consumption during high-frequency operations, as the leakage current in bit arrays dominates, despite efforts to save power in peripheral circuitry by maintaining high voltage levels for both supply nodes.
Innovation Solution
Implementing a dual rail memory system with two supply voltages, where the write voltage (VDDw) is lower than the operation voltage (VDD), reducing saturation current in PMOS transistors and allowing easier data writing, and using retention diodes to minimize leakage current in standby mode by routing current through them instead of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If voltage VDDp is lowered to save power in periphery circuitry, then leakage current in peripheral circuit is reduced, but writing operations fail due to insufficient voltage headroom
Solution Approach 1:
The power supply system is segmented into two independent rails: VDDp for peripheral circuitry and VDDc for bit arrays. This allows independent voltage control - VDDp can be lowered to reduce peripheral leakage current while VDDc remains at sufficient levels to enable reliable writing operations in the bit arrays.
Solution Approach 2:
Different voltage levels are applied to different parts of the memory system based on their specific requirements. The peripheral circuitry receives a lower voltage (VDDp) optimized for low-power standby operation, while the bit arrays receive a higher voltage (VDDc) optimized for reliable read/write operations. This local differentiation resolves the contradiction by matching voltage levels to functional requirements.
2Reliability
If voltage VDDc is kept at high level to enable writing operations, then writing reliability is improved, but power consumption increases due to dominant leakage current in bit arrays
Solution Approach 1:
The memory system operates in periodic cycles alternating between active mode and standby mode. During active mode, VDDc is maintained at high level for reliable operations. During standby mode, VDDc is lowered to reduce leakage current in the bit arrays. This periodic switching resolves the contradiction by temporarily reducing voltage (and thus leakage) when active operations are not occurring.
Solution Approach 2:
The voltage levels VDDp and VDDc are made dynamic rather than static, allowing them to be adjusted based on operational requirements. The system can switch between different voltage states (high/low) for each rail independently, enabling optimization of the trade-off between reliability and power consumption at different times during operation.
3Speed
If both voltage VDDp and VDDc are kept at high level for high frequency operations, then operating speed is improved, but overall power consumption increases
Solution Approach 1:
The power supply is segmented into two independent rails that can be controlled separately. During high-frequency operations, both VDDp and VDDc are maintained at high levels to achieve desired speed. During low-frequency or standby operations, VDDp can be lowered to reduce peripheral leakage current while VDDc is also reduced to minimize bit array leakage. This segmentation enables dynamic power management that resolves the speed-power contradiction.
Solution Approach 2:
The system employs dynamic voltage scaling where the voltage levels of both rails are adjusted in real-time based on operational requirements. For high-speed operations, both voltages are high. For low-power standby, both voltages are lowered. This dynamic adjustment allows the system to optimize the trade-off between operating speed and power consumption depending on the operational phase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption during active operations by lowering the write voltage and utilizing retention diodes to minimize leakage current, thereby saving power and preventing data corruption in un-accessed memory cells.
Implementation Method 1
using retention diodes to minimize leakage current in standby mode by routing current through them instead of transistors
Data Source
AI summary
A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.