Dual Rail Memory Power Supply Using Level Shifters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As technology advances, memory devices face increasing leakage power dissipation due to shrinking device features, which is exacerbated by the need for dual rail memory power supplies to maintain voltage levels for retention and reduce power consumption, leading to inefficiencies in existing dual rail memory power supply schemes.
Innovation Solution
A hybrid dual rail memory power supply scheme is introduced, where the memory arrays and word line driver circuits operate at a higher voltage (VDDM), while the data paths and control circuits operate at both VDDM and a lower voltage (VDD), utilizing level shifters to isolate domains and optimize voltage conversion, thereby achieving balanced performance in speed and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dual rail memory power supply is used to reduce leakage power, then power consumption is reduced, but device complexity increases due to level shifters and voltage domain isolation
Solution Approach 1:
The memory device is divided into different voltage domains: a high-voltage domain (VDDM) for memory arrays requiring retention and a low-voltage domain (VDD) for periphery circuits. This segmentation allows each domain to operate at its optimal voltage, reducing leakage power in the high-voltage domain while maintaining performance in the low-voltage domain.
Solution Approach 2:
Level shifters are introduced as intermediary components between the high-voltage and low-voltage domains. These level shifters convert signal voltages to appropriate domains and isolate the different voltage domains, enabling coexistence of multiple voltage supplies without direct interference.
2Loss of energy
If voltage level is reduced to reduce leakage power, then power consumption decreases, but data retention capability deteriorates
Solution Approach 1:
Different parts of the memory device operate at different voltage levels according to their specific requirements. Memory arrays operate at high voltage (VDDM) to ensure data retention, while periphery circuits operate at low voltage (VDD) to reduce leakage. This local quality approach allows each component to have the voltage level it needs.
3Adaptability or versatility
If level shifters are added to isolate voltage domains, then voltage conversion is enabled, but device complexity and signal delay increase
Solution Approach 1:
Level shifters serve as intermediary components that enable communication between different voltage domains. They convert signal voltages to appropriate domains and isolate the different voltage domains, making the system adaptable to multiple voltage supplies.
Solution Approach 2:
The level shifter creates a voltage-domain-specific copy of the signal. Instead of directly transmitting signals between domains, the level shifter generates an appropriately scaled version of the signal for each domain, enabling voltage conversion with minimal direct coupling.
4Loss of energy
If periphery circuits operate at low voltage while memory arrays operate at high voltage, then leakage power is reduced, but signal conversion complexity increases
Solution Approach 1:
Level shifters are positioned at the interfaces between high-voltage and low-voltage domains to handle signal conversion. This intermediary approach centralizes the complexity of voltage conversion in dedicated components rather than distributing it throughout the entire circuit.
Solution Approach 2:
The circuit is segmented into distinct high-voltage and low-voltage domains with clear boundaries. Level shifters are placed at these boundaries to handle voltage conversion, allowing each domain to operate independently at its optimal voltage while maintaining interface compatibility.
Data Source
AI summary
A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.