Dual Rail Memory Voltage Control Circuit for Write Speed
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Solution Overview
Problem
Current dual rail power supply techniques for SRAM memory arrays face challenges in optimizing write performance due to the need for precise voltage control across bit cells, which affects the efficiency and speed of write operations.
Innovation Solution
The implementation of voltage control circuits that dynamically adjust the power supply voltage (CVDD) levels for each column of bit cells based on the logic levels of the bit lines, using a combination of PMOS and NMOS transistors and regulator circuits to provide a lower voltage level during write operations, thereby enhancing write assist techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual rail power supply techniques are used to improve write performance, then write speed is improved, but voltage control precision requirements increase
Solution Approach 1:
The patent changes the voltage parameter dynamically by switching between a first voltage level (higher) and a second voltage level (lower) based on the write operation state. This parameter change enables improved write speed when the lower voltage is applied, while the voltage level selector circuit ensures precise control by deterministically selecting the appropriate voltage level based on control signals.
2Productivity
If voltage control circuits are added to each column for precise voltage control, then write performance is improved, but device complexity increases
Solution Approach 1:
The voltage level selector circuit serves multiple columns simultaneously by receiving control signals and distributing the appropriate voltage level to multiple column voltage control circuits. This multi-functional approach allows a single control logic to manage voltage levels across multiple columns, reducing overall device complexity while maintaining improved write performance.
3Productivity
If dynamic voltage adjustment is implemented for each column, then write assist efficiency is improved, but chip area increases
Solution Approach 1:
The patent merges the voltage control functionality by implementing a shared voltage level selector circuit that serves multiple columns. Instead of having independent voltage control circuits for each column, the control logic is consolidated and shared, which reduces the total chip area required while maintaining write assist efficiency through dynamic voltage adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves write performance by reducing the voltage level during write cycles, supporting efficient write operations while conserving chip area and reducing the number of voltage control circuits required, thus enhancing memory access performance.
Implementation Method 1
The voltage control circuit coupled to each column is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column
Data Source
AI summary
A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column.