Dual-Rail Logic Circuit with Precharge Gating for DPA Resistance
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Solution Overview
Problem
Current circuits processing security-relevant data are vulnerable to SPS/DPA attacks due to glitches and spurious impulses, especially during transitions between calculation and precharge cycles, which can reveal sensitive information about the current consumption.
Innovation Solution
A dual-rail circuit technology that encrypts input operands and uses a precharge circuit to ensure that output values remain in a precharge state when any input is in the precharge state, preventing early output changes and reducing observability, thereby avoiding glitches and spurious impulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic dual-rail circuit technology is used to protect data from SPS/DPA attacks, then security against side-channel attacks is improved, but design and verification time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-defining standard dual-rail logic cell designs with integrated precharge functionality. These pre-characterized cells can be directly used in security-critical circuits without requiring time-consuming custom design and verification, thus achieving both security and time efficiency.
Solution Approach 2:
The patent changes the operational parameters of dual-rail circuits by implementing synchronized precharge signals that control when precharging occurs. This parameter control allows the circuit to maintain security properties while optimizing performance and reducing verification complexity through predictable timing behavior.
2Reliability
If dynamic dual-rail circuit technology with precharge signals is used, then security is improved, but the circuit cannot be synthesized from a library and is not suited for static timing analyses
Solution Approach 1:
The patent creates universal dual-rail logic cells that serve multiple functions: they provide security through dual-rail operation and precharging, while also being synthesizable from standard libraries and compatible with static timing analysis tools. This multi-functionality resolves the contradiction between security and ease of manufacture.
Solution Approach 2:
The patent segments the dual-rail logic cell into standardized functional blocks that can be independently characterized and verified. This segmentation allows the cells to be treated as modular components that can be synthesized from library elements and analyzed using conventional timing analysis methods.
3Ease of operation
If precharge values are passed through to the output, then the circuit operation is simplified, but security is compromised because precharge values may reveal information about the calculation cycle
Solution Approach 1:
The patent extracts the precharge signal path from the data path by implementing separate control logic that prevents precharge values from being passed to the output during calculation cycles. This separation maintains operational simplicity while eliminating the security vulnerability of precharge value leakage.
4Reliability
If masking technology with encrypted signals is used, then security is improved, but glitches and spurious impulses occur during transitions between calculation and precharge cycles
Solution Approach 1:
The patent applies preliminary anti-action by implementing control logic that anticipates transitions between calculation and precharge cycles. The logic prevents glitches by ensuring that output changes only occur when all inputs have stabilized, thereby counteracting the harmful effect of spurious impulses before they can propagate.
Solution Approach 2:
The patent uses feedback mechanisms where the circuit monitors the state of input signals and adjusts the output accordingly. This feedback ensures that output values are only updated when input conditions are stable, eliminating glitches and spurious impulses while maintaining the security benefits of masking.
Data Source
AI summary
Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or stops impressing the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.