Master-Slave Retention Flip-Flops with Dual-Rail Power Multiplexing
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Solution Overview
Problem
Existing power management techniques for integrated circuits (ICs) face challenges in reducing power consumption while maintaining data retention during power collapse events, as they often require additional memory or complex latch structures, leading to increased area occupancy and resource intensity.
Innovation Solution
The implementation of data retention circuitry with a flip-flop having a master and slave portion, where the slave portion is multiplexed between two power rails, allowing it to remain powered during a power collapse, while the master portion experiences a power collapse, using isolation circuitry to prevent data corruption and a controlled clock signal to maintain data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power is removed from the master portion during power collapse, then power consumption is reduced, but data retention may be lost without additional memory structures
Solution Approach 1:
The flip-flop is divided into master and slave portions with separate power supply arrangements. The master portion can be powered down while the slave portion remains powered, allowing selective power management. This segmentation enables the master portion to consume minimal power during idle periods while the slave portion maintains data retention, resolving the contradiction between power reduction and data reliability.
Solution Approach 2:
Isolation circuitry is introduced as an intermediary between the master and slave portions. This isolation circuitry prevents data corruption during power transitions and ensures that the slave portion's retained data remains intact even when the master portion experiences power collapse. The isolation mechanism acts as a mediator that protects data integrity while enabling power management.
2Reliability
If additional memory or latch structures are used for data retention, then data retention during power collapse is improved, but area occupancy and device complexity increase
Solution Approach 1:
The slave portion of the flip-flop serves multiple functions: it acts as both the data storage element and the retention mechanism during power collapse. By making the slave portion multi-functional, the patent eliminates the need for separate retention memory structures, thereby maintaining data reliability without increasing device complexity or area occupancy.
Solution Approach 2:
The data retention function is merged with the existing slave portion of the flip-flop rather than being implemented as a separate component. This merging approach allows the slave portion to simultaneously perform its normal data storage role and serve as the retention mechanism during power collapse, avoiding additional area occupancy and circuit complexity.
3Reliability
If the slave portion remains powered during power collapse, then data retention is maintained, but power consumption increases compared to complete power down
Solution Approach 1:
The flip-flop is segmented into master and slave portions with independent power management. The master portion is completely powered down during power collapse to minimize energy consumption, while only the essential slave portion remains powered to maintain data retention. This selective segmentation achieves optimal balance between power savings and data reliability.
Solution Approach 2:
Instead of completely powering down the entire flip-flop or maintaining full power, the patent applies partial action by powering down only the master portion while keeping the slave portion minimally powered. This partial power management approach achieves sufficient data retention without the excessive power consumption of complete power maintenance, optimizing the trade-off between energy loss and data reliability.
Data Source
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AI summary
Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.