Dual-Rail Memory Sleep Signal Circuit for Current Spike Prevention
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Solution Overview
Problem
Dual-rail memory circuits experience current spikes due to differential ramp-up rates of voltage supply nodes during transitions out of sleep mode or Power-On Reset events, leading to inefficiency and potential data corruption.
Innovation Solution
A sleep signal generation circuit is implemented to precisely control the transition from sleep mode to operating mode, ensuring supply voltage nodes are stabilized before releasing the sleep signal, thereby preventing current spikes by using a circuit with an input stage, auto-sequencing stage, and output stage to generate an internal sleep signal based on detected voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the first voltage supply node is ramped up quickly after sleep mode, then the system can exit sleep mode faster, but current spikes occur due to differential ramp-up rates between voltage nodes
Solution Approach 1:
The patent applies preliminary action by detecting the power-up status of the first voltage supply node before the actual ramp-up begins. The detection circuit monitors voltage levels and generates appropriate control signals to ensure the first node is properly prepared and stabilized before being ramped up, preventing current spikes caused by premature or uncoordinated voltage transitions.
Solution Approach 2:
The patent implements feedback through a detection circuit that continuously monitors the power-up status of voltage supply nodes. This feedback mechanism provides real-time information about voltage levels to control logic, which then adjusts the ramp-up timing and rate to maintain synchronized transitions between the first and second voltage nodes, eliminating current spikes while preserving fast sleep mode exit.
2Reliability
If the first voltage supply node is ramped up slowly to prevent current spikes, then current stability is improved, but the time to exit sleep mode increases
Solution Approach 1:
The detection circuit performs preliminary assessment of the first voltage supply node's power-up status before initiating the ramp-up sequence. By detecting whether the node is already powered up or still in sleep mode, the system can immediately begin coordinated ramp-up of both voltage nodes together, eliminating the need for slow, cautious ramping while maintaining current stability through synchronized transitions.
Solution Approach 2:
The feedback mechanism provides real-time status information about the first voltage supply node to the control logic. This enables dynamic adjustment of the ramp-up rate - the system can ramp up quickly when conditions permit and maintain stability when needed, optimizing both the speed of sleep mode exit and current stability without compromising either parameter.
3Device complexity
If the same circuitry is used for both sleep mode transitions and power-on events, then device complexity is reduced, but the circuit must handle differential ramp-up rates during first power-up as well
Solution Approach 1:
The patent applies universality by designing a single detection circuit and control mechanism that handles both sleep mode transitions and first power-up events. The detection circuit monitors voltage levels and generates control signals applicable to both scenarios, eliminating the need for separate circuitry while maintaining proper handling of differential ramp-up rates through the same feedback-based coordination mechanism.
Solution Approach 2:
The patent utilizes parameter changes by detecting voltage level parameters of the first supply node and using this information to control the ramp-up process. The detection circuit monitors voltage thresholds and adjusts control signals based on the detected state, enabling the same circuitry to adaptively handle different scenarios (sleep mode exit vs. first power-up) by responding to changing voltage parameters rather than requiring scenario-specific circuitry.
Data Source
AI summary
When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.