Dual-rail SRAM Voltage Segmentation for Speed and Power
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Solution Overview
Problem
Dual-rail SRAMs face significant challenges in maintaining memory access speed when operating at ultra-low supply voltages, which negatively impacts performance while trying to maintain low power consumption and chip area efficiency.
Innovation Solution
The memory device employs a dual-supply voltage configuration, where the memory array and IO circuitry operate at different voltage levels, allowing the control circuit to generate global IO signals efficiently, with the memory array supplied by a higher voltage (VSRAM) for faster access and the IO circuitry by a lower voltage (VCORE) for reduced power consumption and smaller chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the memory array and IO circuitry operate at the same low supply voltage to reduce power consumption and chip area, then power consumption and chip area are reduced, but memory access speed deteriorates significantly
Solution Approach 1:
The patent divides the memory device into two distinct voltage domains: a first voltage domain for the memory array operating at a higher voltage (e.g., 1.2V) and a second voltage domain for the IO circuitry operating at a lower voltage (e.g., 0.8V). This segmentation allows each domain to be optimized independently - the memory array achieves fast access speed with high voltage while the IO circuitry consumes less power with low voltage, resolving the contradiction between speed and power consumption.
2Speed
If the memory array operates at high supply voltage to achieve fast memory access speed, then memory access speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the device into voltage domains so that only the memory array operates at high voltage for fast access, while the IO circuitry operates at low voltage to minimize power consumption. The control circuit manages the interaction between domains, ensuring that high voltage is applied only where necessary for speed-critical operations.
3Use of energy by stationary object
If the entire device operates at ultra-low supply voltage to minimize power consumption, then power consumption is minimized, but memory access time increases greatly
Solution Approach 1:
The patent creates separate voltage domains where the memory array operates at higher voltage to maintain fast access times, while the IO circuitry operates at ultra-low voltage to minimize power consumption. This segmentation resolves the contradiction by applying voltage optimization locally rather than globally across the entire device.
Solution Approach 2:
The patent applies different voltage qualities to different parts of the device based on their specific requirements. The memory array receives higher voltage quality for speed-critical operations, while the IO circuitry receives lower voltage quality sufficient for its functions but optimized for power efficiency. This local quality differentiation resolves the contradiction between overall power minimization and localized speed requirements.
Data Source
AI summary
The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry is configured to access the memory array. The control circuit is configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry, wherein the IO circuitry is supplied by a first supply voltage, the control circuit is supplied by at least a second supply voltage different from the first supply voltage.