Dual RAM Buffer Memory Controller for Data Integrity

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Solution Overview

Problem

Semiconductor memory devices face data integrity issues during sudden power-offs, as volatile RAM used as a write buffer may lose data if power is removed before write data is written to non-volatile flash memory.

Innovation Solution

A storage device with both volatile and non-volatile RAM in the buffer memory, where the memory controller determines the write pattern to select the appropriate RAM for temporary storage, ensuring data integrity by transmitting a host command complete signal after writing to non-volatile RAM before power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile RAM is used as write buffer memory, then write speed and interface speed matching are improved, but data integrity deteriorates when power is lost

Engineering Contradiction:

Improvewrite speedVSAvoiddata integrity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The buffer memory is segmented into two distinct parts: volatile RAM for high-speed write operations and non-volatile RAM for data integrity protection. This segmentation allows each part to fulfill its specific function optimally while working together as a unified buffer system.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Non-volatile RAM acts as an intermediary between the volatile RAM and the flash memory. It temporarily holds data that needs to be protected from power loss, serving as a bridge that ensures data integrity during the transfer process.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If non-volatile RAM is used as write buffer, then data integrity is improved during power loss, but write speed deteriorates due to slower write performance

Engineering Contradiction:

Improvedata integrityVSAvoidwrite speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the buffer memory have different quality characteristics: volatile RAM provides high-speed access for normal operations, while non-volatile RAM provides data persistence for critical protection. Each region's quality is optimized for its specific purpose.

Inventive Principle:

Principle #3Local quality

3Speed

If volatile RAM is used for buffering, then access speed is improved, but data loss risk increases during sudden power-off

Engineering Contradiction:

Improveaccess speedVSAvoiddata loss

Core Design Contradiction:

SpeedVSLoss of information

Solution Approach 1:

The system performs preliminary action by copying data from volatile RAM to non-volatile RAM before power loss can occur. The memory controller continuously monitors and protects data in the buffer, ensuring that critical information is preserved in advance.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If dual RAM buffer system is implemented, then data integrity is improved, but device complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidbuffer memory structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The volatile RAM and non-volatile RAM are merged into a unified buffer memory structure that is managed by a single memory controller. This integration allows the system to benefit from both memory types while maintaining a relatively simple overall architecture.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The buffer memory system serves multiple functions: it provides high-speed buffering through volatile RAM, data protection through non-volatile RAM, and seamless data transfer management through the memory controller. This multi-functionality reduces the need for separate dedicated components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8918580B2Storage device with buffer memory including non-volatile RAM and volatile RAM

Publication Date: 2014.12.23 SAMSUNG ELECTRONICS CO LTD

AI summary

A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM.