Dual-Ramp Clock Synchronization Circuit for Non-50% Duty Cycles
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Solution Overview
Problem
Existing clock generation circuits face challenges in synchronizing internal and external clock signals, particularly when the external clock has a duty cycle other than fifty percent, and existing synchronization techniques like phase-locked loops (PLL) require additional silicon area and increase implementation complexity.
Innovation Solution
A dual-ramp clock generation circuit that synchronizes an internal clock signal with an external clock signal by dividing the external clock's frequency to generate synchronized clock signals with any desired duty cycle, using a dual-ramp generator, d-flip flop, logic circuits, a latch, and a multiplexer to ensure synchronization without the limitations of PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loops (PLL) are used for clock signal synchronization, then clock signals can be synchronized, but additional silicon area is required and implementation complexity increases
Solution Approach 1:
The patent extracts the essential synchronization function from the complex PLL architecture, implementing only the necessary dual-ramp generation and comparison logic. This removes unnecessary components while retaining the core synchronization capability, thereby reducing silicon area and implementation complexity.
Solution Approach 2:
The patent creates a simplified copy of the clock generation function using dual-ramp circuits that replicate the timing behavior needed for synchronization without requiring the full PLL infrastructure. This allows synchronization with reduced complexity by copying only the essential timing characteristics.
2Reliability
If phase-locked loops (PLL) are used for clock signal synchronization, then clock signals can be synchronized, but additional silicon area is required
Solution Approach 1:
The patent extracts the essential synchronization function from the complex PLL architecture, implementing only the necessary dual-ramp generation and comparison logic. This removes unnecessary components while retaining the core synchronization capability, thereby reducing silicon area and implementation complexity.
Solution Approach 2:
The dual-ramp circuit is designed to perform multiple functions: generating the clock signal, providing synchronization capability, and adapting to different duty cycles. This multi-functionality eliminates the need for separate dedicated synchronization circuits, reducing overall silicon area.
3Reliability
If existing synchronization techniques are used, then clock signals can be synchronized, but they are limited to fifty percent duty cycles
Solution Approach 1:
The patent implements dynamic duty cycle adjustment by allowing the dual-ramp generation circuit to adapt its operation based on the incoming clock signal characteristics. The circuit can dynamically adjust to different duty cycles (50%, 33%, 66%, etc.) while maintaining synchronization, making the system versatile rather than fixed.
Solution Approach 2:
The patent changes the operational parameters of the dual-ramp circuit to accommodate different duty cycles. By adjusting the ramp generation and comparison thresholds, the circuit can synchronize with external clocks of varying duty cycles without requiring different hardware configurations, thereby improving adaptability.
Data Source
AI summary
Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.