Dual-Rate ECC Parity for Faster SLC Reads and Error Correction
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Solution Overview
Problem
Current data storage devices, such as solid state drives (SSDs), face performance bottlenecks due to limited correction capability in parity encoding schemes, which either use too many parity bits or require time-consuming reconstruction during reads, especially during single level cell (SLC) reads.
Innovation Solution
The implementation of a dual parity construction matrix and an incremental parity construction matrix, which include a full parity form and a reduced parity form, allowing for adaptive use of parity bits based on conditions, with the second parity portion being 0 in the reduced form, and arranged in block triangular or block diagonal constructions to optimize data transfer and decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a lower amount of parity bits is used during SLC read, then data transfer speed is improved, but correction capability deteriorates
Solution Approach 1:
The parity bits are segmented into two distinct portions: first parity bits and second parity bits. The first parity portion contains bits essential for basic error correction, while the second parity portion contains additional bits for enhanced correction capability. During SLC read operations, only the first parity portion is transferred, achieving fast data access. When full correction capability is needed, both portions are transferred together.
Solution Approach 2:
The system applies partial action by transferring only a subset of the total parity bits (the first parity portion) during fast SLC read operations. This partial transfer provides sufficient correction capability for typical errors while dramatically improving transfer speed. The full parity set can be transferred when exceptional correction capability is required.
2Reliability
If tunable ECC scheme is used with adaptive length and code-rate, then correction capability is improved, but device complexity increases
Solution Approach 1:
Instead of changing the length and code-rate parameters of the entire ECC code, the invention changes the parameter of how many parity bits are transferred by setting the second parity portion to zero. This simple parameter change (transmitting 0 or all parity bits) achieves adaptive correction capability without the complexity of multiple ECC configurations.
3Reliability
If parity puncturing scheme is used with longer ECC data, then correction capability is improved, but decoding time increases
Solution Approach 1:
The parity bits are pre-organized into two portions during encoding, with the first parity portion containing bits that can independently provide correction capability. This preliminary organization allows the decoder to work with a smaller, pre-selected set of parity bits during fast reads, reducing decoding time while maintaining adequate correction capability.
Data Source
AI summary
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.