Dual RC-Timed ESD Clamp Architecture for IC Protection

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Solution Overview

Problem

Existing ESD protection mechanisms for integrated circuits are inadequate in addressing both fast and slow electrostatic discharge events, with current solutions either failing to protect against longer-lasting events or compromising efficiency during normal power-up.

Innovation Solution

A two-clamp RC-timed architecture that includes a high current clamp for short-duration ESD events and a low current clamp for longer events, ensuring protection against both fast and slow transients while minimizing current draw during normal power-up.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the RC time constant is extended to protect against slow ESD events, then protection duration is improved, but current draw during normal power-up increases excessively

Engineering Contradiction:
Improveprotection against slow ESD eventsVSAvoidcurrent draw during power-up
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The protection function is segmented between two clamps with different time constants. The first clamp handles fast events with minimal power consumption, while the second clamp handles slow events. This segmentation allows each clamp to be optimized for its specific function, preventing excessive current draw during normal operation while maintaining protection against slow ESD events.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit dynamically selects which clamp activates based on the characteristics of the incoming ESD event. Fast events trigger the first clamp, while slower events trigger the second clamp. This dynamic response ensures that the circuit only draws high current when absolutely necessary for protection, minimizing power consumption during normal power-up and operation.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The two-clamp scheme effectively protects integrated circuits from ESD events of varying durations with minimal impact on efficiency, providing enhanced manufacturing yields and improved protection against a broader range of ESD scenarios.

Implementation Method 1

an RC-timed high current voltage clamp configured to switch on during an ESD event and discharge a first level of ESD-generated current to ground until the RC-timed high current voltage clamp switches off

Methodology Applied
Scientific EffectRC time constant: Capacitance

Implementation Method 2

Electrostatic discharge (ESD) refers to the discharge of a short burst of high current that results from a build up of static charge

Methodology Applied
Scientific EffectElectrostatic discharge: Electrostatic Discharge

Data Source

PatentUS7518846B1ESD protection method for low-breakdown integrated circuit
Publication Date: 2009.04.14 MAXIM INTEGRATED PROD INC
  • US7518846B1 patent drawing
  • US7518846B1 patent drawing
  • US7518846B1 patent drawing

AI summary

An ESD protection device has a multi-stage RC-timed architecture to turn on quickly and sink current for a relatively long time period. For example, a high power voltage clamp and a low power voltage clamp coupled in parallel to protect internal circuitry of an integrated circuit. The high power clamp turns on during the first few microseconds of an ESD event, and sinks current for a brief period of time, during which the low power clamp turns on as well. Once the high power clamp turns off, the low power clamp continues to sink current until a safe level is reached.