Dual RCD Chip Design for Memory Signal Loading Reduction
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Solution Overview
Problem
The integration of high performance memory with small form factor and less expensive X4 memory chips poses a challenge due to increased loading on command and chip select signal wires, which can compromise signal integrity.
Innovation Solution
The implementation of a dual register clock driver (RCD) chip design that doubles the number of command and chip select signals, distributing the load evenly across two RCD chips, thereby maintaining signal integrity and reducing the load on individual signal wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If X4 memory chips are used to reduce cost and form factor, then memory chip cost and size are reduced, but the loading on command and chip select signal wires increases
Solution Approach 1:
The patent divides the memory module into multiple ranks organized in a hierarchical structure with bank groups, banks, and sub-banks. This segmentation allows the command and chip select signals to be distributed across multiple signal wires rather than all memory chips receiving the same signals simultaneously, thereby reducing the loading on individual signal wires while accommodating X4 memory chips.
2Quantity of substance
If more memory chips are integrated per rank, then memory capacity increases, but signal integrity deteriorates
Solution Approach 1:
The patent introduces a hierarchical ranking system with multiple levels (bank groups, banks, sub-banks) that organizes memory chips in a multi-dimensional structure. This allows signals to be routed through intermediate levels rather than directly to all chips, maintaining signal integrity while increasing the number of memory chips per rank through additional organizational dimensions.
Data Source
AI summary
An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.