Dual RDL Interposer Structure for Extendible Inter-Chip Wiring
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Solution Overview
Problem
Existing semiconductor technologies for high-speed and high-bandwidth inter-chip communication face challenges due to high costs and limited extendibility from through-silicon via processing and reticle size limits, and require additional bridges for inter-chip transmission.
Innovation Solution
A dual redistribution layer (RDL) interposer structure is fabricated using wet etching along natural crystallographic planes, eliminating the need for Bosch™ or deep reactive ion etching, and incorporating conductive vias filled with copper, with BEOL fine inter-chip wiring in an inorganic dielectric layer and power RDLs in an organic dielectric layer for efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via processing is used, then inter-chip communication is achieved, but fabrication cost increases and extendibility is limited
Solution Approach 1:
The patent divides the interposer structure into two separate redistribution layers (RDLs) with distinct functions: the first RDL handles fine-pitch inter-chip signaling while the second RDL handles power delivery. This segmentation allows each layer to be optimized independently, avoiding the complexity of through-silicon via processing while maintaining reliable inter-chip communication.
Solution Approach 2:
The patent transitions from vertical through-silicon via connections to a planar dual RDL architecture where connections are established through separate conductive layers. This dimensional change from 3D vertical integration to 2D planar integration eliminates the need for deep etching and complex via formation processes.
2Ease of manufacture
If reticle size limits are imposed, then manufacturing is constrained, but extendibility is reduced
Solution Approach 1:
By segmenting the interconnect function into separate first and second RDLs, the patent enables independent optimization of each layer's pitch and dimensions. This allows the structure to be scaled and adapted to different reticle sizes without being constrained by a single unified via design.
3Reliability
If additional bridges are added for inter-chip transmission, then communication capability is improved, but device complexity increases
Solution Approach 1:
The first redistribution layer serves multiple functions simultaneously: it provides fine-pitch inter-chip signaling connections and eliminates the need for additional bridge structures. This multi-functionality reduces overall device complexity while maintaining communication capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a low-cost, high-density, and extendible interposer structure for high-speed and high-bandwidth inter-chip communication, enabling fine wiring for communication and thicker lines for power delivery without additional bridges, reducing fabrication complexity and cost.
Implementation Method 1
etching a semiconductor substrate to expose natural crystallographic planes to form trenches
Implementation Method 2
depositing conductive material within the trenches of the etched semiconductor substrate to form vias
Data Source
AI summary
A method for fabricating a dual redistribution layer (RDL) interposer structure is provided. The method includes etching a semiconductor substrate to expose natural crystallographic planes to form trenches. The method also includes depositing conductive material within the trenches of the etched semiconductor substrate to form vias for an interposer structure. The method includes placing back end of line (BEOL) inter-chip wiring on a top side of the interposer structure using a first RDL. The method includes exposing the vias on a back side of the interposer structure. The method further includes forming power RDLs on a back side of the interposer structure using conductive lines in a dielectric layer.