Dual RDL Stacked Die Packaging With Vertical Wires for Signal Integrity
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Solution Overview
Problem
Double-digit stacked die packages face challenges such as decreased yield, high assembly and testing costs, and longer testing and assembly times, with existing solutions like vertical wire packages increasing package size and reducing signal integrity due to long wire bond lengths.
Innovation Solution
The implementation of semiconductor packages with dual-sided redistribution layers (RDLs) and thin vertical wires, enabling package on package (PoP) integration, which reduces footprint, enhances electrical performance, and allows for rework and design modifications, thereby improving yield and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical wire packages with wire bonds are used to connect package to package, then package connectivity is achieved, but package size increases and signal integrity margin decreases due to long wire bond lengths
Solution Approach 1:
The patent extracts and eliminates the wire bond interconnection method from the package structure. Instead of using wire bonds to connect packages, the invention uses direct substrate integration and embedded conductors within the package substrate itself, removing the harmful long wire bonds that degraded signal integrity while maintaining electrical connectivity between stacked packages.
Solution Approach 2:
The patent transitions from horizontal wire bond connections to vertical through-substrate conductor connections. By changing the dimensional orientation of the interconnects from lateral (horizontal wire bonds) to vertical (through-substrate vias and conductors), the signal path length is dramatically reduced, improving signal integrity while enabling higher density stacking.
2Quantity of substance
If double-digit stacked die packages are assembled, then memory capacity increases, but yield decreases significantly
Solution Approach 1:
The patent implements preliminary testing and validation of individual die stacks before final package assembly. By performing pre-assembly electrical testing, bonding validation, and functional verification on smaller stacks (e.g., 2-4 dies) before scaling to double-digit stacks, defects are detected early, preventing propagation through the entire production line and significantly improving final yield.
Solution Approach 2:
The patent segments the double-digit stacked die assembly process into modular stages. Instead of assembling all dies in one step, the process is divided into incremental stacking phases where smaller validated stacks are assembled first, then combined. This segmentation allows for intermediate testing and quality control checkpoints, reducing the compounding effect of defects and improving overall yield.
3Quantity of substance
If double-digit stacked die packages are assembled, then memory capacity increases, but assembly and testing costs increase significantly
Solution Approach 1:
The patent merges multiple testing operations into unified test protocols that can validate entire stacked die assemblies in a single test cycle. By integrating electrical continuity testing, functional validation, and interconnect verification into combined test sequences, the number of separate testing steps is reduced, decreasing both time and cost while maintaining comprehensive quality assurance for high-capacity stacks.
Solution Approach 2:
The patent implements self-diagnostic and self-validation capabilities within the stacked die package structure. Embedded sensors, built-in self-test (BIST) circuits, and automated identification features allow the package to report its own status, interconnect integrity, and functional performance, reducing the need for external manual testing and lowering assembly and testing costs.
4Quantity of substance
If double-digit stacked die packages are assembled, then memory capacity increases, but testing and assembly staging time increases
Solution Approach 1:
The patent establishes continuous flow assembly and testing processes where stacks move through production stages without interruption. Automated pick-and-place machines and in-line testing equipment enable uninterrupted assembly and validation, eliminating idle time between operations. The continuous process maintains constant production rhythm, reducing total staging time while accommodating increased stack complexity.
Solution Approach 2:
The patent implements rapid testing protocols and expedited validation procedures that quickly verify critical parameters without compromising quality. Compressed test sequences, parallel validation of multiple parameters simultaneously, and fast fail-safe mechanisms allow the system to rapidly assess stack integrity and functionality, minimizing the time required for testing and staging high-capacity stacked die packages.
Data Source
AI summary
Embodiments include a semiconductor package, a package on package system, and a method of forming the semiconductor package. The semiconductor package includes a first redistribution layer, a stack of dies on the first redistribution layer, a second redistribution layer over the stack of dies and the first redistribution layer, and a plurality of interconnects coupled to the stack of dies and the first and second redistribution layers. The interconnects may extend substantially vertical from a top surface of the first redistribution layer to a bottom surface of the second redistribution layer. The semiconductor package may also include a mold layer between the first redistribution layer and the second redistribution layer. The plurality of interconnects may be through mold vertical wire interconnects. The first and second redistribution layers may be dual-sided redistribution layers. The semiconductor package may further include adhesive layers coupled to the stack of dies.