Dual-Read NVM Soft Read for Destructive Read Error Correction
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Solution Overview
Problem
Existing memory systems with destructive read characteristics, such as 3D crosspoint memory, face challenges in efficiently correcting errors without increasing costs or causing performance bottlenecks due to re-reads, especially when bit errors occur.
Innovation Solution
Implementing a dual-read approach with different reference voltages to identify and assign lower confidence values to bits that change between reads, and using error correction codes to correct errors based on these confidence values, thereby reducing the need for additional ECC parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is implemented using traditional ECC memory with additional devices, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines error correction functionality with the existing NVM device structure by implementing dual-read operations within the same memory array. Instead of adding separate ECC devices, the system merges error detection and correction into the read operation itself by performing two reads with different reference voltages and comparing results, thereby improving reliability without increasing device complexity
Solution Approach 2:
The NVM device performs self-diagnosis and self-correction by comparing results from dual reads with different reference voltages. The system identifies bits that change between reads as potential errors and uses confidence values to guide correction, allowing the memory to service its own error correction needs without external ECC hardware
2Reliability
If re-read operations are performed to correct errors, then error correction capability is improved, but productivity decreases due to performance bottlenecks
Solution Approach 1:
The system performs a preliminary dual-read operation with different reference voltages during the initial read cycle. By identifying potential error bits and assigning confidence values before the main data processing, the system prepares correction information in advance, allowing error correction to occur without requiring additional re-read operations that would bottleneck productivity
Solution Approach 2:
The patent dynamically adjusts reference voltages during read operations to optimize both error detection and read speed. By using different reference voltages for the two reads and adaptively selecting confidence values based on voltage differences, the system maintains high read performance while enabling effective error correction without fixed performance penalties
3Reliability
If more ECC parity bits are used to increase error correction rate, then reliability is improved, but loss of information increases due to reduced data capacity
Solution Approach 1:
The patent changes the parameter of reference voltage to enable error detection and correction without adding parity bits. By varying reference voltages between two read operations and comparing results, the system extracts error information from the existing data bits themselves, maintaining full data capacity while achieving improved error correction rates
Solution Approach 2:
The patent uses confidence values as an intermediary mechanism to bridge error detection and correction. Instead of requiring additional parity bits, the system generates confidence values that indicate the reliability of each bit based on dual-read comparison, allowing the ECC decoder to prioritize correction efforts without reducing data storage capacity
Data Source
AI summary
Techniques and mechanisms for supporting error correction of data accessed in a non-volatile (NVM) memory. In an embodiment, a memory controller performs reads each of the same codeword from the NVM, wherein a first read is based on a first reference voltage, and a second read is based on a second reference voltage. Based on the first read and the second read, confidence values are assigned each to respective bits of the codeword. Error correction comprises applying a weights to respective bits of the codeword based on the confidence values. In other embodiments, a relatively low confidence value is assigned to codeword bits that have a different value for the first read and the second read.