Complementary XOR SRAM Cell With Dual Read Bit Lines for Full Adders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SRAM cells, particularly those used in in-memory computational devices, cannot perform certain logic functions like exclusive OR (XOR) operations efficiently, which are essential for search operations and floating-point calculations, and they require multiple clock cycles for full adder operations.
Innovation Solution
A 3-port SRAM complementary XOR cell design with two read bit lines is implemented, allowing for two logic computations per clock cycle and enabling full adder operations in a single clock cycle by using cross-coupled inverters and specific transistor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional SRAM cells are used for in-memory computation, then basic Boolean operations (AND, OR, NAND, NOR) can be performed, but certain logic functions like XOR cannot be implemented
Solution Approach 1:
The patent applies universality by designing an SRAM cell that can perform multiple logic functions including XOR, XNOR, AND, OR, NAND, and NOR operations. The cell achieves this through two read bit lines coupled to cross-coupled inverters, allowing the same hardware structure to execute diverse boolean operations without requiring separate specialized circuits for each function.
Solution Approach 2:
The patent introduces a new dimension to conventional SRAM cells by adding a second read bit line (RBLb) in addition to the standard read bit line. This dimensional expansion enables the cell to perform XOR and XNOR operations by utilizing both bit lines simultaneously, transforming a single-function cell into a multi-functional computational unit.
2Speed
If conventional SRAM cells are used for full adder operations, then computation can be performed, but it requires multiple clock cycles reducing computational speed
Solution Approach 1:
The patent applies continuity of useful action by enabling full adder operations to complete in a single clock cycle. The dual read bit line architecture allows both sum and carry operations to be executed simultaneously without requiring multiple sequential steps, eliminating idle time and maintaining continuous computational action throughout the clock cycle.
Solution Approach 2:
The patent applies preliminary action by pre-configuring the cross-coupled inverter structure and dual bit line connections before computation begins. This pre-arranged architecture ensures that all necessary logic paths are already established and ready to execute full adder operations immediately when inputs are applied, eliminating setup delays and enabling single-clock-cycle completion.
3Productivity
If search operations using XOR logic are implemented, then efficient data comparison can be performed, but conventional SRAM cells lack the capability to perform XOR operations
Solution Approach 1:
The patent applies universality by designing an SRAM cell that can perform multiple logic functions including XOR, XNOR, AND, OR, NAND, and NOR operations. The cell achieves this through two read bit lines coupled to cross-coupled inverters, allowing the same hardware structure to execute diverse boolean operations without requiring separate specialized circuits for each function.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.