Dual-Reference Clock Generator for Low-Jitter Frequency Locking
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Solution Overview
Problem
Existing frequency locked loops (FLLs) in digital audio signal processing face challenges in generating a high-quality clock signal with low jitter, especially when the input clock is of poor quality or experiences degradation during transmission, leading to noise, distortion, and spurious tones, and require minimal external components for economic implementation in integrated circuit form.
Innovation Solution
A clock generator using a frequency locked loop architecture with dual input clock signals and digital filters to produce an output clock signal with reduced jitter, incorporating a numerically controlled oscillator driven by filtered error signals, and utilizing on-chip oscillators for minimal external components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a frequency locked loop is used to generate a clock signal at a multiple of the input clock frequency, then the output clock frequency can be accurately controlled, but the jitter of the output clock increases due to poor quality input clock or transmission degradation
Solution Approach 1:
The patent segments the frequency multiplication process into multiple stages using a cascade of frequency locked loops. Each stage multiplies the frequency by a smaller factor, which reduces the accumulation of jitter and distortion in each individual stage compared to a single high-multiplication stage. This segmented approach maintains frequency accuracy while reducing overall output jitter.
Solution Approach 2:
The patent introduces an intermediary low-jitter clock source that is phase-locked to the input clock. This intermediary clock serves as a clean reference signal that mediates between the poor quality input clock and the output clock generation process, providing a stable basis for frequency multiplication that reduces jitter propagation.
2Reliability
If digital filters are added to reduce jitter in the frequency locked loop, then the output clock quality improves, but the device complexity and number of external components increases
Solution Approach 1:
The patent replaces analog mechanical filters with digitally implemented filters within the frequency locked loop. These digital filters are integrated into the existing digital logic of the FLL, eliminating the need for separate external analog filter components while effectively reducing jitter and improving output clock quality.
Solution Approach 2:
The patent designs the digital filters to serve multiple functions: they filter jitter from the frequency error signal, shape the loop bandwidth response, and can be programmably adjusted for different application requirements. This multi-functionality reduces the need for separate dedicated components for each function, simplifying the overall device.
3Measurement precision
If multiple input clock signals are processed through separate frequency comparators and filters, then the clock synchronization and jitter reduction improve, but the power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating and selective activation of frequency comparators and filters based on the operational mode and input clock availability. When multiple input clocks are present, the system dynamically selects which processing paths are active, reducing unnecessary power consumption while maintaining synchronization accuracy for the active clock sources.
Solution Approach 2:
The patent employs clock switching mechanisms that can discard certain input clock processing paths when they are not needed for the current operational mode. The system recovers power by selectively disabling frequency comparators and filters for inactive clock inputs, while maintaining the capability to quickly reactivate them when needed, thus reducing average power consumption.
Data Source
AI summary
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.