Dual-Reference Clock Generator for Low-Jitter Frequency Locking
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Solution Overview
Problem
Existing frequency locked loops (FLLs) used in clock generators for integrated circuits face challenges in generating high-quality clock signals with low jitter, especially in digital audio processing, where poor input clock quality and intermittent data transmission can lead to noise, distortion, and clock slippage, requiring minimal external components and efficient power management.
Innovation Solution
A clock generator design incorporating two input clock signals, with one having lower jitter and higher frequency accuracy, and a numerically controlled oscillator driven by filtered error signals from dual digital filters, ensuring the output clock signal has the desired frequency accuracy and low jitter, even in intermittent data scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input clock signal is used in the FLL, then the device complexity is reduced, but the output clock signal quality (jitter and frequency accuracy) deteriorates when the input clock quality is poor
Solution Approach 1:
The patent divides the clock signal processing into two separate input channels: a first input clock signal for frequency control and a second input clock signal for jitter reduction. This segmentation allows each input to serve a specific function, with the first providing frequency accuracy and the second providing low jitter, thereby resolving the contradiction between device complexity and output clock quality.
Solution Approach 2:
The patent introduces an intermediary mechanism that combines two input clock signals through the FLL architecture. The first input clock signal serves as a reference for frequency multiplication, while the second input clock signal acts as a clean reference for jitter reduction. This intermediary approach allows the system to achieve high-quality output without requiring a single perfect input clock.
2Device complexity
If a single input clock signal is used, then the device complexity is reduced, but the reliability of clock synchronization deteriorates in intermittent data transmission scenarios
Solution Approach 1:
The patent segments the clock reference function into two independent inputs: the first input clock signal maintains frequency relationships during normal operation, while the second input clock signal provides a stable reference that ensures synchronization reliability during intermittent data transmission. This segmentation allows the system to maintain reliable synchronization without increasing overall device complexity.
3Manufacturing precision
If two digital filters are used to process error signals from two input clocks, then the output clock quality is improved, but the device complexity increases
Solution Approach 1:
The patent segments the error signal processing into two dedicated digital filters: a first digital filter processes the frequency error from the first input clock, and a second digital filter processes the phase error from the second input clock. This segmentation allows each filter to be optimized for its specific function, achieving low jitter output while maintaining manageable device complexity through functional specialization.
4Speed
If a numerically controlled oscillator is used to multiply the first input clock frequency, then the desired output frequency is achieved, but the output jitter increases due to poor input clock quality
Solution Approach 1:
The patent introduces a second input clock signal as an intermediary clean reference that mediates between the frequency multiplication function and the jitter reduction requirement. The NCO multiplies the first input clock frequency to achieve the desired output frequency, while the second input clock signal serves as a clean reference that reduces jitter through the second digital filter, thereby resolving the contradiction between frequency multiplication and jitter control.
Data Source
AI summary
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.