Two-Stage Impedance Calibration Circuit for Linear Memory Termination

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Solution Overview

Problem

As semiconductor memory device operational speeds increase, signal distortion due to impedance mismatch becomes severe, requiring an accurate impedance calibration operation to maintain termination impedance independent of process, voltage, and temperature variations.

Innovation Solution

An impedance calibration circuit that includes a first code generation circuit, a second code generation circuit, and a target impedance code generation circuit, using reference resistors to generate codes for forming resistances and achieving a target impedance value, with a termination driver forming the impedance based on these codes, reducing driver area and capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional impedance calibration circuit uses a single reference resistor and code generation method, then the circuit structure is simple, but it cannot provide reliable termination impedance for wide-range target impedance values and has large driver area and capacitance

Engineering Contradiction:
Improvetermination impedance reliabilityVSAvoidcode generation circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the code generation process into multiple stages: a first code generation circuit generates initial codes using a first reference resistor, and a second code generation circuit refines these codes using a second reference resistor. This segmentation allows the system to handle wide-range target impedance values reliably while managing circuit complexity through functional decomposition.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary calculation process where the second code generation circuit uses both the first code and second code as inputs to generate a final target impedance code. This intermediary step acts as a mediator that combines information from multiple reference resistors to achieve accurate impedance calibration across wide ranges.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the driver area and capacitance are reduced, then the signal distortion is minimized, but the ability to provide accurate impedance calibration across wide-range target impedance values may be compromised

Engineering Contradiction:
Improvesignal distortionVSAvoidimpedance calibration precision
Core Design Contradiction:
Object-affected harmful factorsVSMeasurement precision

Solution Approach 1:

The patent changes the resistance parameters by using two different reference resistors with different resistance values. The first reference resistor is used for generating initial codes, and the second reference resistor is used for refining the codes. This parameter variation enables the system to achieve accurate impedance calibration across wide-range target impedance values while using compact drivers with reduced area and capacitance.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If a single reference resistor is used for impedance calibration, then the circuit area is reduced, but the linearity between code and impedance value deteriorates for wide-range target impedance values

Engineering Contradiction:
Improvecircuit areaVSAvoidcode-impedance linearity
Core Design Contradiction:
Area of stationary objectVSStability of the object's composition

Solution Approach 1:

The patent creates a composite calibration system by combining outputs from two different reference resistors. The first code from the first reference resistor and the second code from the second reference resistor are combined in the second code generation circuit to produce the final target impedance code. This composite approach maintains code-impedance linearity across wide ranges while keeping the overall circuit area compact.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11502687B2Impedance calibration circuit and memory device including the same
Publication Date: 2022.11.15 SAMSUNG ELECTRONICS CO LTD
  • US11502687B2 patent drawing
  • US11502687B2 patent drawing
  • US11502687B2 patent drawing

AI summary

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.