Dual-Reference LO Clock Generation for Low Phase Noise Tuning
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Solution Overview
Problem
Modern multi-carrier RF systems face challenges in creating low Phase Noise LO clock sources with wide tuning ranges and fine frequency resolution, as existing technologies struggle to integrate low Phase Noise over broad bandwidths and require high-Q resonators that are expensive and difficult to fabricate using standard IC technologies.
Innovation Solution
The use of a combination of Integer-N and Fractional-N PLLs with a mixer to combine high Phase Noise and low Phase Noise clock signals, where the low Phase Noise source is integrated with MEMS or BAW resonators, allowing for the generation of low Phase Noise LO clocks suitable for multi-carrier RF systems, covering frequencies from 700 MHz to 2 GHz with 100 kHz resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If high-Q resonators are used to generate low Phase Noise clock signals, then Phase Noise is reduced, but manufacturing cost and fabrication difficulty increase
Solution Approach 1:
The system segments the clock generation function into two separate references: a first reference clock signal with good frequency stability but high Phase Noise, and a second reference clock signal with low Phase Noise but potential frequency drift. Each reference serves a specific purpose in the overall clock generation architecture, allowing the system to achieve low Phase Noise without requiring difficult-to-fabricate high-Q resonators.
Solution Approach 2:
A Phase-Locked Loop (PLL) circuit acts as an intermediary that combines the two reference clock signals. The PLL uses the frequency stability of the first reference and the low Phase Noise characteristics of the second reference to generate a synthesized clock signal that achieves low Phase Noise performance without requiring expensive high-Q resonators, thus resolving the manufacturing difficulty while maintaining Phase Noise reduction.
2Adaptability or versatility
If wide tuning range is implemented in LO clock generators, then frequency flexibility improves, but Phase Noise performance deteriorates
Solution Approach 1:
The system dynamically switches between different reference clock sources and PLL configurations depending on the required output frequency range. For frequencies requiring wide tuning, the system utilizes the flexible second reference clock signal, while for frequencies requiring optimal Phase Noise performance, it switches to the stable first reference clock signal. This dynamic adaptation allows the system to maintain low Phase Noise across a wide tuning range.
3Measurement precision
If fine frequency resolution is achieved through high multiplication factors, then frequency precision improves, but Phase Noise multiplication increases
Solution Approach 1:
The system changes the reference clock frequency parameter to achieve fine frequency resolution without high multiplication factors. By using the second reference clock signal with lower Phase Noise and appropriate PLL division ratios, the system can achieve 100 kHz frequency resolution while avoiding the Phase Noise multiplication that would occur with high-N frequency synthesis, thus resolving the contradiction between frequency precision and Phase Noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in integrated, cost-effective LO clock generators with reduced Phase Noise, meeting the requirements of modern RF systems by filtering out Phase Noise and providing flexible frequency tuning, thus enhancing the Signal-to-Noise Ratio and information-carrying bandwidth.
Implementation Method 1
a Phase-Locked Loop (PLL) circuitry having a PLL bandwidth selected to filter out the first clock signal Phase Noise
Implementation Method 2
with a mixer, combining the intermediate clock signal with the second clock signal to generate a target clock signal
Data Source
AI summary
A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.