Dual-Reference PLL with Adaptive Divider for Low-Noise Locking
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Solution Overview
Problem
Integrated circuit phase-locked loops using low-frequency reference oscillators face limitations in bandwidth, requiring off-chip components or digital filters, and are susceptible to reference noise due to large feedback divide ratios.
Innovation Solution
Incorporating a stable high-frequency reference oscillator and a feedback divider ratio adjustment circuit that scales the output signal of a voltage-controlled oscillator, allowing for a phase-locked loop with small feedback divide ratios and sufficient low bandwidth, using a sigma delta modulator to adjust the feedback divider ratio until synchronization is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a low-frequency reference oscillator is used to save cost and power, then the system cost and power consumption are reduced, but the bandwidth of the phase-locked loop is limited and requires off-chip components or digital filters
Solution Approach 1:
The patent segments the reference signal processing into two paths: a low-frequency reference signal path for power saving and a high-frequency synthesized path for adequate bandwidth. The feedback divider ratio adjustment circuit separately processes signals at different frequencies to achieve both low power consumption and sufficient bandwidth without requiring off-chip components.
Solution Approach 2:
The patent introduces an intermediary high-frequency reference oscillator and feedback divider ratio adjustment circuit that mediates between the low-frequency reference oscillator and the VCO. This intermediary allows the system to maintain low power consumption from the low-frequency reference while achieving adequate bandwidth through the high-frequency synthesis path.
2Ease of manufacture
If a low-frequency reference oscillator is used, then cost and power are saved, but off-chip components or digital filters are required to achieve sufficiently low bandwidth
Solution Approach 1:
The patent merges the low-frequency reference oscillator with a high-frequency reference oscillator and feedback divider ratio adjustment circuit into a single integrated on-chip system. This combination eliminates the need for off-chip components while maintaining both cost-effectiveness and adequate bandwidth control.
Solution Approach 2:
The feedback divider ratio adjustment circuit performs multiple functions: it synthesizes high-frequency signals from low-frequency references, adjusts feedback divider ratios dynamically, and provides adequate bandwidth without requiring separate off-chip filters or components. This multi-functionality reduces overall system complexity and component count.
3Productivity
If a stable high-frequency reference oscillator is incorporated, then adequate bandwidth is achieved, but the complexity of the phase-locked loop increases
Solution Approach 1:
The patent employs dynamic adjustment of the feedback divider ratio based on the phase error detected between the VCO output and the reference signal. This dynamic adaptation allows the system to achieve adequate bandwidth and locking performance without requiring a permanently complex high-frequency reference circuit, reducing overall system complexity.
Solution Approach 2:
The system changes the feedback divider ratio parameter dynamically to optimize performance. By adjusting this parameter based on detected phase errors and synchronization status, the system achieves adequate bandwidth without permanently increasing circuit complexity, as the complexity only arises temporarily during the adjustment phase.
4Stability of the object's composition
If large feedback divide ratios are used with low-frequency references, then the loop bandwidth is reduced, but the system becomes susceptible to reference noise
Solution Approach 1:
The patent performs preliminary frequency synthesis by the feedback divider ratio adjustment circuit before the signal enters the main PLL loop. By pre-scaling the reference frequency to an appropriate level, the system avoids using excessively large feedback divide ratios in the main loop, thereby maintaining both adequate bandwidth and reduced susceptibility to reference noise.
Data Source
AI summary
A phase-locked loop has a stable high frequency reference oscillator to provide a stable high frequency reference signal that has reference frequency that is a small submultiple of a generated frequency of a voltage controlled oscillator within the phase-locked loop. An adjustable output frequency feedback circuit has with a feedback divide ratio that is approximately the small submultiple and adjusts the feedback ratio such that the generated frequency of the voltage controlled oscillator is locked to a stable low frequency reference input signal. The feedback divide ratio is adjusted as a function of a required ratio change value that is a function of a current phase error of the generated frequency of a voltage controlled oscillator and the stable low frequency reference input signal and a phase error derivative. The phase error derivative is a difference of the current phase error and a previous phase error.