Dual-Reference PLL Bandwidth Control for Stable Wireless Audio Clocks
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Solution Overview
Problem
Conventional phase-locked loop (PLL) based clock generators in wireless audio systems face challenges in maintaining stable clock signals, especially when wireless communication links degrade, leading to audible errors and increased power consumption due to complex mitigation mechanisms.
Innovation Solution
A PLL clock generator system that uses a combination of a reference clock and a data clock from a communications module to generate stable and jitter-free clock signals, employing a fractional divider and delta-sigma modulator to adjust the PLL core, thereby avoiding the need for asynchronous sample rate converters and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL based clock generators are used to provide stable clocking in wireless audio systems, then clock stability is improved, but the system loses lock when wireless communication links degrade, causing audible errors
Solution Approach 1:
The patent introduces an intermediary mechanism (buffer and counter system) between the PLL and the wireless communication link. This intermediary allows the PLL to maintain its lock by providing a buffer of captured data packets and using counters to track packet indices, enabling the system to bridge timing gaps when the wireless link degrades without causing the PLL to lose lock.
Solution Approach 2:
The system implements beforehand cushioning by pre-capturing and buffering data packets before link degradation occurs. The buffer stores a predetermined number of packets, and the system uses packet index tracking to resume synchronization after interruptions, providing a cushion that prevents lock loss during temporary link failures.
2Reliability
If mitigation mechanisms are incorporated to prevent PLL lock loss, then reliability is improved, but system complexity and power consumption significantly increase
Solution Approach 1:
The patent segments the mitigation function into distinct, manageable components: a buffer for storing data packets, counters for tracking packet indices, and control logic for managing the transition between locked and unlocked states. This segmentation reduces overall system complexity by organizing the mitigation mechanism into modular, independent elements that can be implemented efficiently.
3Reliability
If mitigation mechanisms are incorporated to prevent PLL lock loss, then reliability is improved, but power consumption significantly increases
Solution Approach 1:
The system employs periodic action by using a finite state machine that transitions between distinct operational states (locked, unlocked, recovering) based on the wireless link status. This periodic state-based control allows the system to activate mitigation mechanisms only when needed, rather than continuously, thereby reducing power consumption while maintaining reliability during link degradation events.
Data Source
AI summary
Disclosed herein are systems and methods for improved performance of phase-locked loop based clock generators, particularly in the context of wireless audio. A PLL clock generator includes a PLL core configured to receive a module reference clock provided by a communications module and generate a subsystem data clock corresponding to a module data clock of the communications module; and a data clock tracker module configured to receive the module data and subsystem data clocks and determine a corresponding data clock correction factor. The bandwidth of the PLL core may be dynamically changed thereby enabling both fast and very precise settling. The PLL core may use a low jitter frequency reference for the phase detector while an a synchronous and jitter-prone audio sample clock is used to ensure a mean frequency of the PLL core tracks the audio sample clock.