Dual-Reference PLL Phase Tracking for High Bandwidth, Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional phase-locked loop (PLL) designs face a conflict between achieving high tracking bandwidth and low jitter peaking, as high loop gain required for fast acquisition times amplifies jitter, leading to jitter peaking, while loop filtering to reduce jitter peaking results in low tracking bandwidth and increased jitter accumulation.
Innovation Solution
A dual-reference phase-locked loop that utilizes both rising and falling edges of an incoming reference clock to produce a center phase signal, allowing for higher stability, bounded jitter amplification, and increased tracking bandwidth without sacrificing either goal, by centering the tracking phase between the two reference phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high loop gain is used to achieve high tracking bandwidth and fast acquisition times, then tracking bandwidth is improved, but jitter peaking increases
Solution Approach 1:
The patent segments the single reference phase into two separate reference phases (rising edge and falling edge), creating two independent phase tracking loops. This segmentation allows each loop to operate with reduced gain requirements while maintaining overall high tracking bandwidth, thereby reducing jitter peaking while preserving speed performance.
Solution Approach 2:
The patent transitions from single-phase tracking to dual-phase tracking by adding a temporal dimension (using both rising and falling edges). This dimensional expansion enables the system to achieve high tracking bandwidth through parallel processing of multiple reference edges, reducing the need for excessive loop gain and thereby mitigating jitter peaking.
2Object-generated harmful factors
If loop filtering is added to reduce jitter peaking, then jitter peaking is reduced, but tracking bandwidth decreases and acquisition time increases
Solution Approach 1:
By segmenting the tracking into two parallel loops (one for rising edge, one for falling edge), the patent eliminates the need for heavy loop filtering in each individual loop. The combined output achieves high tracking bandwidth while each loop operates with lower gain, naturally reducing jitter peaking without sacrificing speed.
3Device complexity
If single-reference phase tracking is used, then device complexity is low, but both high tracking bandwidth and low jitter peaking cannot be achieved simultaneously
Solution Approach 1:
The patent divides the reference clock into two separate phase references (rising and falling edges), creating two independent tracking loops. This segmentation enables simultaneous achievement of high tracking bandwidth and low jitter peaking, as each loop can be optimized independently while their combined output provides superior overall performance.
Solution Approach 2:
The patent merges the outputs of two parallel phase tracking loops (rising edge tracker and falling edge tracker) to produce the final tracking phase. This combination allows the system to achieve high tracking bandwidth and low jitter peaking simultaneously, overcoming the limitations of single-reference tracking while adding minimal complexity.
Data Source
AI summary
A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.