Dual-Reference Feedback Circuit for Dead-Zone-Free Signal Locking

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Solution Overview

Problem

Digital feedback systems, such as phase-locked loop circuits and ZQ calibration circuits, often experience dead zones and resolution errors due to variations in target value signals, which affect the accuracy of output levels in nonvolatile memory devices.

Innovation Solution

A feedback system with a lock signal generation circuit that uses two reference signals to generate a lock signal by counting time and rounding the quotient of count data, eliminating dead zones and reducing resolution errors by adjusting the input signal level accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single reference signal is used for comparison in a feedback system, then the system structure is simple, but dead zones appear in the output signal when the target value varies

Engineering Contradiction:
Improvereference signal structureVSAvoidoutput signal accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The single reference signal is segmented into two reference signals (first reference signal and second reference signal) with different levels. This segmentation allows the system to cover a wider range of target values without dead zones, as the ambiguous signal indicates which reference signal level the input signal is between, enabling continuous tracking.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a one-dimensional comparison (single reference signal) to a two-dimensional comparison space (two reference signals with different levels). This dimensional expansion creates a more robust comparison framework where the ambiguous signal provides additional information about the input signal's position relative to reference levels, eliminating dead zones.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Stability of the object's composition

If digital feedback control is applied to nonvolatile memory devices, then the system can maintain output levels, but resolution errors occur due to target value signal variations

Engineering Contradiction:
Improveoutput level maintenanceVSAvoidresolution error
Core Design Contradiction:
Stability of the object's compositionVSMeasurement precision

Solution Approach 1:

The system employs a feedback mechanism where the lock signal, generated based on the ambiguous signal from comparing the input signal with two reference signals, controls the code signal to adjust the output. This feedback loop continuously corrects resolution errors by detecting when the input signal level stabilizes between reference levels and adjusting the output accordingly, improving measurement precision while maintaining stability.

Inventive Principle:
Principle #23Feedback

3Productivity

If the input signal level is allowed to vary freely, then the system responds dynamically to target value changes, but dead zones appear when the target value varies

Engineering Contradiction:
Improveresponse dynamicsVSAvoidoutput accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary action by pre-establishing two reference signals at different levels before the actual comparison process. The ambiguous signal is generated in advance to indicate which reference level range the input signal falls into, allowing the system to proactively adjust the code signal and prevent dead zones before they occur, maintaining both dynamic response and accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10483955B2Feedback system and method of operating the same
Publication Date: 2019.11.19 SK HYNIX INC
  • US10483955B2 patent drawing
  • US10483955B2 patent drawing
  • US10483955B2 patent drawing

AI summary

The feedback system includes an input signal generation circuit configured to output an input signal having a level corresponding to a code signal inputted thereto and a lock signal generation circuit configured to output the code signal for controlling a level of the input signal using two reference signals, to generate count data acquired by counting time from when the level of the input signal reaches between levels of the two reference signals to when the level of the input signal becomes higher or lower than the level of any one of the two reference signals, and to output a lock signal for fixing the level of the input signal after time corresponding to a rounded value of a quotient of the count data divided by 2.