Dual-Reference ZQ Calibration Circuits for Impedance Matching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Impedance mismatch in semiconductor integrated circuit devices due to variations in power supply voltage and temperature leads to signal reflection and distortion, compromising high-speed data transmission.
Innovation Solution
An on-die dual reference ZQ calibration system using internal resistor circuits with coarse, fine, and temperature trim circuits, along with a comparator and offset correction, to adjust impedance and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ZQ calibration using external calibration resistor is used, then impedance matching can be achieved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the calibration resistor from external location and integrates it internally on the chip. The internal calibration resistor circuit (204) replaces the external calibration resistor, eliminating the need for external components while maintaining calibration functionality. This extraction principle resolves the contradiction by moving the calibration function inside the chip boundary, reducing external area requirements.
Solution Approach 2:
The patent merges multiple functions into integrated circuits on the chip. The calibration resistor circuit (204), calibration logic (208), and impedance adjustment circuits are combined into a single integrated system. This merging eliminates discrete external components and reduces overall chip area while maintaining full calibration capability.
2Reliability
If conventional ZQ calibration using external calibration resistor is used, then impedance matching can be achieved, but power consumption increases
Solution Approach 1:
The calibration function is extracted from external components and integrated internally. The internal calibration resistor circuit (204) performs calibration without requiring external power connections, reducing overall power consumption while maintaining calibration precision.
Solution Approach 2:
The integrated calibration system is self-contained and self-powered through internal circuitry. The calibration logic (208) and resistor circuit (204) work together autonomously using internal power distribution, eliminating the need for external power sources and reducing overall system power consumption.
3Object-affected harmful factors
If output driver impedance is adjusted to match external transmission line, then signal reflection is reduced, but impedance varies with power supply voltage and temperature
Solution Approach 1:
The patent implements a feedback mechanism where the calibration logic (208) continuously monitors and adjusts the impedance of output drivers (202) and on-die termination circuits (206). The calibration system measures actual impedance conditions and dynamically adjusts circuit parameters to maintain optimal matching despite variations in power supply voltage or temperature, thereby reducing signal reflection while maintaining stability.
Solution Approach 2:
The patent makes the impedance adjustment dynamic rather than static. The calibration logic (208) can adjust impedance parameters in real-time based on operating conditions. This dynamic adjustment capability allows the system to adapt to changing power supply voltage and temperature conditions, maintaining impedance stability and minimizing signal reflection across varying environmental conditions.
4Productivity
If peak-to-peak voltage is reduced to decrease supply current, then signal transmission delay is minimized, but signal becomes more susceptible to noise and impedance mismatch
Solution Approach 1:
The calibration logic (208) provides continuous feedback adjustment of impedance parameters to optimize signal integrity at low voltage levels. By dynamically adjusting the impedance of output drivers (202) and termination circuits (206), the system compensates for increased susceptibility to noise and reflection that occurs at reduced voltage levels, maintaining reliable high-speed transmission.
Solution Approach 2:
The patent changes impedance parameters dynamically to optimize performance at different voltage levels. The calibration system adjusts resistance and impedance values based on operating conditions, allowing the circuit to maintain optimal signal integrity even when peak-to-peak voltage is reduced for faster transmission and lower power consumption.
Data Source
AI summary
An apparatus is provided that includes a first pull-up driver circuit coupled to a first calibration node, an internal resistor circuit and first input/output pad on an integrated circuit die, a second pull-up driver circuit coupled to a second calibration node and second input/output pad on the integrated circuit die, a third pull-up driver circuit coupled to a third calibration node, a comparator including a first input terminal selectively coupled to the first calibration node, the second calibration node and the third calibration node, and a second input terminal coupled to a reference voltage, and circuitry configured to trim the reference voltage to compensate for a comparator offset, and trim an impedance of the internal resistor circuit by comparing a voltage on the first calibration node and the trimmed reference voltage. The trimmed impedance of the internal resistor circuit substantially equals a desired impedance of the third pull-up driver circuit.