Dual-Region Memory Architecture for Enhanced Data Retention
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Solution Overview
Problem
Conventional memory systems face challenges in maintaining data retention characteristics and reliability, particularly in three-dimensional flash memory structures, where the retention characteristics of data in certain regions are compromised due to charge leakage and threshold voltage shifts.
Innovation Solution
The memory system employs a dual-region architecture with distinct memory cell configurations, where the second memory cell region utilizes multiple memory transistors and a specific word line configuration to enhance data retention, and a controller manages operations to optimize writing, reading, and erasing processes based on cold data storage principles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional NAND flash memory structure is used to increase storage capacity, then storage density is improved, but data retention characteristics deteriorate due to charge leakage and threshold voltage shifts
Solution Approach 1:
The memory cell array is divided into two distinct regions: a first region with memory cells having first word lines and a second region with memory cells having second word lines. This segmentation allows different retention enhancement techniques to be applied to different regions, resolving the contradiction between high storage density and data retention characteristics.
Solution Approach 2:
Different word line configurations are applied to different regions of the memory cell array. The second region uses multiple second word lines connected to gates of memory cells in a configuration that reduces charge leakage, while the first region uses a conventional configuration. This local differentiation allows retention enhancement in specific areas without sacrificing overall storage capacity.
2Speed
If multiple word lines are selected simultaneously for reading or writing, then operation speed is improved, but control complexity increases
Solution Approach 1:
The row decoder is configured to dynamically select between single word line selection and multiple simultaneous word line selection based on the operation type. For reading operations, multiple second word lines can be selected simultaneously to increase throughput, while for writing operations, single word line selection maintains precision. This dynamic adaptability resolves the contradiction between speed and control complexity.
Data Source
AI summary
A memory system includes a memory device including a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, and a controller configured to control an operation of the memory device. The memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.