Dual Register Clock Driver Memory Subsystem Architecture
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Solution Overview
Problem
Existing memory module architectures are limited by the number of supportable memory devices due to the physical capacity of signaling drivers, particularly the subchannel driver circuitry, which restricts the size of memory modules and does not support multiple register clock driver chips.
Innovation Solution
Implementing a memory subsystem with two register clock driver devices to increase the number of output drivers, allowing for the support of a greater number of memories by providing independent subchannel driver circuits synchronized by a common clock signal, enabling contemporaneous signaling of command and address information across multiple subchannels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single register clock driver chip is used, then the device complexity is reduced, but the number of supportable memory devices is limited
Solution Approach 1:
The patent divides the register clock driver functionality into multiple separate driver chips (first register clock driver and second register clock driver). Each driver chip contains independent subchannel driver circuits that can be individually configured to drive different numbers of memory devices. This segmentation allows the system to support more memory devices than a single driver chip could handle, while each individual driver chip maintains manageable complexity.
2Quantity of substance
If multiple subchannel driver circuits are added, then the number of supported memories increases, but the signaling synchronization becomes more difficult
Solution Approach 1:
The patent merges multiple subchannel driver circuits from different register clock driver chips into a unified signaling system. The first and second register clock drivers are configured to operate together, with their subchannel driver circuits working in parallel to drive command and address information to multiple memory devices simultaneously. This merging approach increases the number of supported memories while maintaining signaling synchronization through coordinated operation of the multiple drivers.
Data Source
AI summary
A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.