Dual Register File Data Paths for Mixed Multiply Execution
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Solution Overview
Problem
Current DSP cores face challenges in achieving higher computational capacity, particularly in floating-point and complex linear algebra operations, and require increased processing power, which existing architectures struggle to efficiently address.
Innovation Solution
A processor architecture is designed with dual execution units for handling both fixed-point and floating-point multiply instructions, along with a register file that enables simultaneous execution and data paths for efficient operand handling, reducing logic levels and signal propagation delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate multipliers and data paths are used for fixed-point and floating-point operations, then operational accuracy is maintained, but device complexity and area requirements increase
Solution Approach 1:
The patent combines fixed-point and floating-point multiplication capabilities into a single execution unit with a unified data path. The register file is organized into groups and sub-groups that can be simultaneously accessed, allowing both data types to share the same computational resources while maintaining operational accuracy through dedicated control logic for each operation type.
Solution Approach 2:
The execution unit is designed with universal multiply functionality that can handle both fixed-point and floating-point operations. The register file structure with groups and sub-groups enables the same hardware resources to serve multiple purposes, reducing overall device complexity while maintaining the ability to perform both operation types with appropriate precision.
2Reliability
If separate multipliers and data paths are used for fixed-point and floating-point operations, then operational reliability is maintained, but power consumption increases
Solution Approach 1:
By merging fixed-point and floating-point multiplication into a single execution unit with shared data paths, the patent reduces the total number of active components during operation. The register file's group and sub-group structure enables efficient resource sharing, lowering dynamic power consumption while maintaining operational reliability through controlled access mechanisms.
Solution Approach 2:
The execution unit dynamically configures its data paths and register access based on the operation type (fixed-point or floating-point). This dynamic adaptation allows the system to activate only the necessary components for each operation, reducing unnecessary power consumption while maintaining full operational reliability for both data types.
3Device complexity
If traditional register file architecture is used, then simplicity is maintained, but processing speed and computational capacity are limited
Solution Approach 1:
The register file is segmented into groups and sub-groups, allowing simultaneous access to multiple registers through different data paths. This segmentation enables parallel operand retrieval for both fixed-point and floating-point operations, significantly increasing processing speed while maintaining a structured, manageable architecture that doesn't excessive complexity.
Solution Approach 2:
The patent introduces a hierarchical organization of registers with groups and sub-groups, adding a dimensional structure to the register file. This multi-level organization enables concurrent access from multiple execution units through different data paths, boosting computational capacity and processing speed without proportionally increasing architectural complexity.
4Area of stationary object
If traditional data path architecture is used, then area requirements are reduced, but execution time increases
Solution Approach 1:
The data path is segmented into multiple concurrent paths that can simultaneously service different operation types. The register file's group and sub-group structure enables parallel data retrieval, reducing execution time while keeping each individual data path compact enough to minimize overall chip area requirements.
Solution Approach 2:
The architecture enables continuous operation by allowing multiple data paths to work simultaneously on different operations. While one path processes fixed-point operations, another can handle floating-point operations, eliminating idle time and reducing overall execution time without requiring proportionally larger chip area.
Data Source
AI summary
A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.