Dual-Register Page Buffer for Continuous NAND Flash Data Reading

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Solution Overview

Problem

Conventional NAND-type flash memory devices face inefficiencies in continuous page reading operations due to busy periods occurring at page or block boundaries, leading to potential data discontinuity and increased read time, especially when handling large amounts of pages.

Innovation Solution

A non-volatile semiconductor memory device with a page buffer system that includes two data registers and a transmission gate, allowing for simultaneous data transmission and error correction between the registers, enabling continuous data output without discontinuities at page boundaries by dividing data transmission into halves and using transmission transistors to manage data flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transmitted from the first data register to the second data register in a conventional single-register system, then data reading can be performed, but busy periods occur at page or block boundaries causing data discontinuity and increased read time

Engineering Contradiction:

Improvedata reading speedVSAvoidbusy period duration

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent divides the data register into two separate data registers (first data register and second data register) to segment the data storage function. This segmentation allows data transmission to occur in parallel with error correction operations, eliminating busy periods and enabling continuous data output without interruption at page or block boundaries.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary data transmission from the first data register to the second data register before the conventional busy period would occur. By anticipating and executing data transmission in advance during periods when error correction is being performed, the system ensures data is ready for immediate output, eliminating waiting time and maintaining continuous data flow.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If a single data register is used for storing and transmitting data, then device complexity is reduced, but data transmission must wait for error correction completion causing discontinuity

Engineering Contradiction:

Improvecontinuous data transmissionVSAvoidpage buffer structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The page buffer is segmented into two distinct data registers (first and second data registers) with separate functions. The first data register receives data from the memory array while the second data register transmits data to the external device. This functional segmentation enables parallel operations and continuous data flow, justifying the increased structural complexity through significant performance improvement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second data register acts as an intermediary between the first data register and the external device. It receives data from the first register, performs error correction on it, and then transmits the corrected data externally. This intermediary structure allows error correction to be performed on data already received while new data is simultaneously being received, enabling continuous operation.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If error correction is performed on data before transmission, then data accuracy is improved, but transmission must wait causing idle time

Engineering Contradiction:

Improvedata accuracyVSAvoidwaiting time for error correction

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Data transmission from the first data register to the second data register is performed as a preliminary action before error correction completes on the original data. This allows the system to pipeline operations: while error correction is being performed on data in the first register, that same data is simultaneously being transmitted to the second register, eliminating idle waiting time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent maintains continuity of useful action by ensuring that data transmission never waits for error correction to complete. The dual-register architecture allows error correction and data transmission to occur simultaneously and continuously without interruption, maximizing system utilization and eliminating idle periods.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS9218888B2Non-volatile semiconductor memory data reading method thereof

Publication Date: 2015.12.22 WINBOND ELECTRONICS CORP

AI summary

A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.