Dual-Function Data Register With Integrated Program Verify
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Solution Overview
Problem
Existing non-volatile memory technologies, such as anti-fuse memories, require a second data register for program verification, leading to increased circuit area and manufacturing costs due to complex logic and iterative programming cycles.
Innovation Solution
A dual-function data register with integrated program verify functionality, utilizing a master-slave flip-flop configuration and phase-adjustable clock signals, allows concurrent data storage and verification without the need for a second register, enabling serial and parallel data interfacing and automatic program inhibit logic to prevent re-programming of successfully programmed bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second data register is used for program verification, then verification reliability is improved, but device complexity and circuit area increase
Solution Approach 1:
The patent merges the program verification function into the existing data register by utilizing its internal latches and clock signals. The data register's first latch stores program data while the second latch stores read data, and the verification logic uses these same components to compare data and generate status signals, eliminating the need for a separate verification register.
Solution Approach 2:
The data register is designed to perform multiple functions: storing program data, storing read data, performing program verification through data comparison, and generating status signals. This multi-functional design allows a single register to replace what would traditionally require two separate registers, reducing circuit area while maintaining verification reliability.
2Reliability
If a second data register is used for program verification, then verification accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines the verification functionality into the existing data register structure, using its latches and clock signals for both data storage and verification operations. This eliminates the need for additional registers and reduces the overall circuit complexity, leading to lower manufacturing costs while maintaining verification accuracy.
Solution Approach 2:
The data register performs verification operations using its own internal resources (latches and clock signals) without requiring external verification hardware. The verification logic uses the register's inherent components to compare program data with read data and generate status signals, making the system self-sufficient and reducing manufacturing complexity.
3Reliability
If complex verification logic is implemented, then verification reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements verification through a feedback mechanism where the data register continuously compares program data with read data and generates status signals based on the comparison results. This feedback loop provides reliable verification while keeping the logic simple, as the verification is performed automatically through the register's operational cycle rather than through complex external verification logic.
Data Source
AI summary
A dual function serial and parallel data register with integrated program verify functionality. The master and slave latching circuits of the dual function data register can concurrently store two different words of data. In a program verify operation, the master latch stores program data and the slave latch will receive and store read data. Comparison logic in each register stage will compare the data of both latches, and integrate the comparison result to that of the previous register stage. The final single bit result will indicate the presence of at least one bit that has not been programmed. Automatic program inhibit logic in each stage will prevent successfully programmed bits from being re-programmed in each subsequent reprogram cycle. Either data word can be serially clocked out by selectively starting the shift operations on either the low or high active logic level of a clock signal.