Dual Register File Instruction Execution to Avoid Wave Conflicts

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Solution Overview

Problem

The existing graphics processors face inefficiencies due to read-write conflicts in common register files between consecutive instructions, necessitating the insertion of NOP instructions, which degrade execution performance.

Innovation Solution

Implementing a method where instructions are executed by alternating between two common register files for even and odd-numbered waves, allowing source operands to be stored in different files, reducing the need for NOP instructions and improving execution efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single common register file is used for all waves, then device complexity is reduced, but read-write conflicts occur between consecutive instructions requiring NOP insertion which decreases execution efficiency

Engineering Contradiction:
Improveinstruction execution efficiencyVSAvoidregister file structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The common register file is segmented into multiple banks (first common register file and second common register file) that can be independently accessed. This segmentation allows simultaneous read-write operations on different banks without conflict, eliminating the need for NOP instructions while maintaining reasonable device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of access by adding bank selection capability to the register file structure. By incorporating a bank selection unit that can switch between first and second common register files based on wave number parity, the system enables parallel access patterns that resolve conflicts without significantly increasing overall structural complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If NOP instructions are inserted to resolve read-write conflicts, then reliability of data access is improved, but execution time increases due to additional instruction cycles

Engineering Contradiction:
Improvedata access correctnessVSAvoidinstruction execution time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The bank selection unit pre-determines which common register file bank to use based on the wave number before instruction execution begins. By preparing the appropriate bank in advance and switching to it proactively, the system ensures correct data access without requiring post-conflict NOP delays, thus maintaining reliability while reducing time loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The bank selection unit acts as an intermediary between the instruction execution unit and the common register files. It mediates access conflicts by intelligently routing even-numbered waves to the first bank and odd-numbered waves to the second bank, ensuring data correctness without introducing time-consuming NOP instructions.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the wave controller transmits instructions in each even-numbered clock cycle, then instruction throughput is increased, but read-write conflicts in the common register file increase requiring more NOP instructions

Engineering Contradiction:
Improveinstruction throughputVSAvoidregister file conflicts
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system implements periodic action by alternating the use of first and second common register file banks based on the parity of wave numbers. Even-numbered waves periodically access the first bank while odd-numbered waves periodically access the second bank, creating a rhythmic pattern of access that maintains high throughput while systematically avoiding conflicts.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

By segmenting the common register file into multiple banks and assigning different banks to different wave groups, the patent enables the wave controller to transmit instructions at high frequency without generating conflicts. The segmentation isolates access paths so that increased transmission frequency does not lead to increased conflict frequency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260056743A1Instruction execution method and apparatus, computer device, storage medium, and computer program product
Publication Date: 2026.02.26 GLENFLY TECH CO LTD
  • US20260056743A1 patent drawing
  • US20260056743A1 patent drawing
  • US20260056743A1 patent drawing

AI summary

The present disclosure relates to an instruction execution method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: receiving an instruction transmitted by a wave controller in each even-numbered clock cycle, wherein two instructions received in two consecutive even-numbered clock cycles correspond to an even-numbered wave and an odd-numbered wave respectively; acquiring a source operand from a first common register file when the instruction corresponds to the even-numbered wave, or acquiring a source operand from a second common register file when the instruction corresponds to the odd-numbered wave; and executing the instruction based on the source operand. With the method, the execution efficiency can be improved.