Dual Fast Slow Release Storage Controller Write Mechanism
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Solution Overview
Problem
In high-data-throughput environments, storage systems face challenges with power interruptions and write failures during data writing to non-volatile memory, as the SRAM buffer in the controller may not be large enough to hold data temporarily, and retaining task IDs in the host's command queue can slow performance.
Innovation Solution
Implementing a dual fast release and slow release response system, where the storage system sends separate instructions to release task IDs from the command queue and data from the buffer, allowing the host to store data in its buffer until successfully written to non-volatile memory, and reattempt writes if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage system keeps a copy of data in volatile memory to handle power interruptions or write failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the data retention function into two separate components: volatile memory for temporary buffering and non-volatile memory for persistent storage. This segmentation allows the system to maintain reliability through multiple storage layers while managing complexity by dividing responsibilities between different memory types with distinct characteristics.
Solution Approach 2:
The volatile memory acts as an intermediary between the host and non-volatile memory, temporarily holding data during write operations. This intermediary layer protects against write failures by providing a safety buffer, while the controller manages the coordination between volatile and non-volatile memory to handle power interruptions and write errors.
2Reliability
If the SRAM buffer in the controller is made larger to hold data temporarily, then reliability is improved, but device complexity and resource requirements increase
Solution Approach 1:
Instead of increasing buffer size in a single dimension (SRAM capacity), the patent adds a temporal dimension by implementing a two-phase write process with separate completion indicators. Data can be acknowledged as received (first completion) and then as successfully written to non-volatile memory (second completion), allowing reliable operation with smaller buffers.
Solution Approach 2:
The host performs preliminary data retention by maintaining copies in its own buffer until write completion is confirmed. This preliminary action shifts the buffering burden from the controller's SRAM to the host's memory resources, reducing the controller's buffer size requirements while maintaining reliability through coordinated error handling.
3Reliability
If task IDs are retained in the host's command queue to ensure data integrity, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent segments the task ID retention period into two distinct phases: the command queue phase (until data transfer completion) and the buffer retention phase (until write completion). By separating these phases and using different identification mechanisms (task IDs vs. buffer IDs), the system maintains reliability for critical operations while improving throughput by allowing command queue slots to be reused immediately after data transfer.
Solution Approach 2:
The host discards task IDs from the command queue after data transfer completion, recovering these identifiers for reuse in subsequent commands. This discarding and recovering process improves productivity by increasing command queue throughput, while reliability is maintained through the continued retention of buffer IDs and the dual-completion indicator system that tracks write status.
Data Source
AI summary
A storage system and method for dual fast release and slow release responses are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to receive, from a host, a write command and data to be written in the non-volatile memory. The host comprises a command queue storing an identifier for the write command and a buffer storing a copy of the data. In response to storing the data in the volatile memory, the controller is configured to instruct the host to remove the identifier for the write command from the host's command queue. In response to successfully writing the data in the non-volatile memory, the controller is configured to instruct the host to remove the copy of the data from the host's buffer. Other embodiments are provided.