Dual Reset-Branch SAR ADC for Shorter CMOS Sensor Row Time
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Solution Overview
Problem
As sensor frame rates and resolutions increase, the row time for pixel readout and ADC conversion in CMOS image sensors becomes challenging due to increased parasitic capacitance, leading to longer settling times and higher power consumption, with existing solutions like ping-ponging between ADCs being costly in terms of area and prone to offsets.
Innovation Solution
Implementing a pipelined analog-to-digital conversion using dual reset-side branches that overlap with the previous conversion phase, allowing for faster operation without duplicating the entire ADC structure, specifically in SAR ADCs with a single signal-side branch and two reset-side branches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the row time is decreased to support higher frame rates and resolutions, then the productivity is improved, but the settling time increases due to increased parasitic capacitance
Solution Approach 1:
The patent performs reset sampling in advance during the previous conversion phase, so that when the current pixel conversion is needed, the reset level is already ready. This preliminary action eliminates the need to wait for reset sampling to complete, thereby reducing the critical path settling time while maintaining high frame rates
2Productivity
If faster settling from pixel outputs is required to shrink pixel readout time, then the productivity is improved, but the power consumption increases
Solution Approach 1:
The patent implements pipelined operation where reset sampling, signal sampling, and ADC conversion occur in overlapping continuous phases. The reset branch operates continuously during conversion phases, and the signal branch operates continuously during reset sampling phases, eliminating idle time and reducing the need for high-power fast settling circuits
3Productivity
If the ADC conversion time is shrunk to support shorter row times, then the productivity is improved, but the area and power required increase
Solution Approach 1:
The patent divides the ADC operation into two independent branches: a reset branch and a signal branch. Each branch can operate independently and in parallel, allowing the conversion process to be segmented into overlapping phases. This segmentation enables faster effective conversion rate without requiring a single high-speed ADC that would consume more area and power
4Productivity
If ping-ponging between two ADCs is used to pipeline pixel readout and ADC conversion, then the productivity is improved, but the area increases due to duplication of circuitry
Solution Approach 1:
The patent merges the reset sampling function and signal sampling function into a single integrated ADC structure with two branches sharing common resources. The reset branch and signal branch share the same comparator, capacitor array, and control logic, allowing pipelined operation without duplicating the entire ADC circuitry. This merging achieves area efficiency while maintaining the productivity benefits of pipelining
Data Source
AI summary
Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.