Dual Resistive Layer Semiconductor Layout for Gate Resistance Selection

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Solution Overview

Problem

Existing semiconductor elements with resistive layers require multiple bonding wires, increasing chip size and limiting the ability to set appropriate resistance values for semiconductor modules.

Innovation Solution

A semiconductor element with two resistive layers of different resistance values, each connected to a separate external connection electrode, covered by a passivation film with asymmetrical openings, allowing for reduced bonding wires and precise resistance value selection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If two resistive layers with different resistance values are provided to enable resistance value selection, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveresistance value selectionVSAvoidstructure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies asymmetry by providing openings in the passivation film with different shapes corresponding to different resistive layers. Specifically, a first opening with a first shape exposes a first external connection electrode connected to a first resistive layer, while a second opening with a second shape (different from the first shape) exposes a second external connection electrode connected to a second resistive layer. This asymmetric opening design enables resistance value selection without requiring additional switching components, thereby improving adaptability while maintaining simple device structure.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If multiple bonding wires are used to connect electrodes, then electrical connection reliability is improved, but chip size increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidchip size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the resistance value selection function from the electrical connection path by using asymmetric openings in the passivation film to expose different external connection electrodes. This allows the selection between first and second resistive layers without requiring additional bonding wires or switching components, thereby maintaining electrical connection reliability while reducing chip size.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If resistance value is specifically set for each semiconductor module, then performance reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveperformance reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements dynamics by enabling post-manufacturing selection of resistance values through the asymmetric opening structure. The different shaped openings allow selective electrical connection to either the first or second resistive layer with different resistance values, providing flexible adaptation to different semiconductor module performance requirements without requiring separate manufacturing processes for each resistance value.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12451425B2Semiconductor element with resistive layers having different resistance values
Publication Date: 2025.10.21 FUJI ELECTRIC CO LTD
  • US12451425B2 patent drawing
  • US12451425B2 patent drawing
  • US12451425B2 patent drawing

AI summary

A semiconductor element includes: a first resistive layer; a second resistive layer provided separately from the first resistive layer and having a resistance value different from that of the first resistive layer; a first external connection electrode electrically connected to one end of the first resistive layer; a second external connection electrode provided separately from the first external connection electrode and electrically connected to one end of the second resistive layer; and a passivation film provided to cover the first and second external connection electrodes and having a first opening and a second opening to which top surfaces of the first and second external connection electrodes are partly exposed, wherein the first opening and the second opening having planar patterns with shapes different from each other.