Dual Resistive Memory Cell for Expanded Window
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Solution Overview
Problem
Existing integrated circuits with resistive memory cells have limited cell windows, making them less reliable and harder to read, and current designs often require increased footprint to achieve larger cell windows.
Innovation Solution
The integration of two resistive memory units in an integrated circuit, where one unit is in electrical communication with the source and the other with the drain of a transistor, along with additional source and bit lines, allows for a larger cell window without increasing the footprint, achieved through specific manufacturing processes involving semiconductor materials and electrode structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single resistive memory unit is used in the memory cell, then the device complexity is reduced, but the cell window is limited (about 10)
Solution Approach 1:
The memory cell is segmented into two separate resistive memory units (first and second resistive units), each with its own bottom electrode, top electrode, and resistive element. This segmentation allows the cell window to be increased from about 10 to about 15 or more, while maintaining manageable device complexity through systematic integration with the transistor.
2Reliability
If the footprint of the resistive memory cell is increased, then the cell window can be enlarged, but the area required for the circuit increases
Solution Approach 1:
The patent integrates two resistive memory units within the same planar footprint by utilizing vertical stacking and shared transistor structures. The first and second resistive units are positioned to share the transistor and associated wiring, effectively increasing the cell window without proportionally increasing the footprint area.
3Reliability
If two resistive memory units are integrated in the memory cell, then the cell window increases (about 15 or more), but the device complexity increases
Solution Approach 1:
The first and second resistive memory units are merged through shared infrastructure including the transistor, source line, and bit line. This merging approach allows the cell window to increase to about 15 or more while controlling device complexity by consolidating common elements rather than fully duplicating all components.
4Reliability
If additional source lines are added to support two resistive units, then the cell window is improved, but the manufacturing complexity increases
Solution Approach 1:
The additional source lines are designed to serve multiple functions: the first source line connects to the first resistive unit while the second source line connects to the second resistive unit, yet both can be controlled through the same bit line and transistor structure. This multi-functionality approach improves the cell window while managing manufacturing complexity through standardized connection patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a cell window approximately 1.9 to 2.7 times larger than traditional single-resistive unit designs, enhancing reading reliability without expanding the circuit's footprint, by utilizing the same transistor size as comparable single-resistive unit circuits.
Implementation Method 1
The resistance of the resistive element can be switched between a high resistance state and a low resistance state, where conductive 'filaments' are presumed to form within the resistive element in the low resistive state, and the conductive 'filaments' are ruptured or broken in the high resistive state. The 'filaments' are presumed to form from a dielectric breakdown where atoms are oxidized in the filament such that the resistance is reduced
Implementation Method 2
The 'filaments' are presumed to form from a dielectric breakdown where atoms are oxidized in the filament such that the resistance is reduced
Data Source
AI summary
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.