Dual-Resolution System Timer for Low-Power ICs
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Solution Overview
Problem
Integrated-circuit devices face challenges in achieving timing accuracy and efficiency due to the transition between low-power and high-power oscillators, leading to difficulties in processor interaction and increased power consumption.
Innovation Solution
The implementation of a system timer with separate low-resolution and high-resolution timers, featuring hardware-based synchronization, allowing continuous monitoring with low-resolution timers and selective enabling of high-resolution timers based on device states, reducing computational burden and enhancing power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If low-power oscillators are used in low-power modes, then power consumption is reduced, but timing accuracy and precision deteriorate
Solution Approach 1:
The timer system is segmented into two independent timer units: a low-resolution timer that operates continuously at low power, and a high-resolution timer that operates selectively when needed. This segmentation allows the system to achieve low power consumption during normal operation while maintaining the capability for high-precision timing when required, resolving the contradiction between power savings and timing accuracy.
2Measurement precision
If high-resolution timers are continuously enabled, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between low-resolution and high-resolution timer operation based on real-time needs. The low-resolution timer operates continuously with minimal power consumption, while the high-resolution timer is dynamically enabled only when precise timing is required. This dynamic operation mode allows the system to optimize the balance between timing accuracy and power consumption, avoiding the continuous high power consumption that would result from keeping the high-resolution timer always on.
3Device complexity
If software-based synchronisation is used between timers, then device complexity is reduced, but processing time and computational burden increase
Solution Approach 1:
The patent replaces software-based synchronisation mechanisms with a hardware-based synchronisation circuit. This hardware circuit automatically synchronises the high-resolution timer to the low-resolution timer when the high-resolution timer is enabled, eliminating the need for complex software calculations and processing. The hardware synchronisation occurs instantly through dedicated circuitry, significantly reducing the transition time and computational burden compared to software-based approaches while maintaining relatively simple device architecture.
Data Source
AI summary
An integrated-circuit device comprises a low-resolution timer and a high-resolution timer. The low-resolution timer comprises a first oscillator that outputs a first clock signal at a first frequency, and a first counter register incremented by the first clock signal. The high-resolution timer comprises a second oscillator that outputs a second clock signal at a second frequency, greater than the first frequency, and a second counter register incremented by the second clock signal. The device operates in one of a plurality of states, including an active state in which both the high-resolution timer and the low-resolution timer are enabled, and a sleep state in which the high-resolution timer is disabled and the low-resolution timer is enabled. The device transitions from the sleep state to the active state by writing a value to the second counter register based on a value held in the first counter register.