Dual-Resonator IC Layout for Compact Time-Digital Conversion

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Solution Overview

Problem

Existing resonator devices face challenges in size reduction and performance degradation due to parasitic resistance and capacitance, especially when multiple resonators are integrated, making it difficult to achieve compact designs while maintaining high processing performance.

Innovation Solution

A resonator device configuration that includes multiple resonators supported by integrated circuit devices with dedicated oscillation circuits and processing circuits, utilizing frequency difference and comparison information to improve processing performance, and incorporating shield lines to reduce noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple crystal oscillators are used in independent packages to generate clock signals, then time-digital conversion can be realized, but device size cannot be reduced

Engineering Contradiction:
Improvetime-digital conversion capabilityVSAvoiddevice size
Core Design Contradiction:
Measurement precisionVSVolume of moving object

Solution Approach 1:

The patent integrates multiple resonators (first resonator and second resonator) and their respective oscillation circuits onto a single integrated circuit device, merging previously separate oscillator packages into one unified device. This integration maintains the capability to generate multiple clock signals for time-digital conversion while significantly reducing the overall device volume by eliminating the need for multiple independent packages.

Inventive Principle:
Principle #5Merging (Combining)

2Volume of moving object

If crystal oscillators are integrated onto an IC chip, then device size is reduced, but parasitic resistance and capacitance increase causing performance degradation

Engineering Contradiction:
Improvedevice sizeVSAvoidperformance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent addresses the parasitic effect problem by carefully designing the spatial arrangement and dimensional layout of resonators and connection paths on the integrated circuit device. By optimizing the physical dimensions and relative positions of components, the patent minimizes the length of clock signal lines and connection paths, thereby reducing parasitic resistance and capacitance while maintaining compact integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Volume of moving object

If one resonator is mounted on the integrated circuit, then compact design is achieved, but arrangement configuration for accommodating two or more resonators is not proposed

Engineering Contradiction:
Improvedevice sizeVSAvoidarrangement configuration for multiple resonators
Core Design Contradiction:
Volume of moving objectVSAdaptability or versatility

Solution Approach 1:

The patent divides the integrated circuit device into distinct functional regions, with separate support portions for the first resonator and second resonator. This segmentation allows each resonator to be independently positioned and supported, enabling compact arrangement of multiple resonators on the same device while maintaining proper spacing and connection paths for each oscillator circuit.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables a compact resonator device with enhanced processing performance by utilizing frequency difference information and reducing noise interference, leading to improved time-digital conversion accuracy and frequency correction capabilities.

Implementation Method 1

an integrated circuit including a piezoelectric resonator, a clock signal generation circuit, and a CPU is mounted on a chip board

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Implementation Method 2

incorporating shield lines to reduce noise interference

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS10666195B2Resonator device, electronic apparatus, and vehicle
Publication Date: 2020.05.26 SEIKO EPSON CORP
  • US10666195B2 patent drawing
  • US10666195B2 patent drawing
  • US10666195B2 patent drawing

AI summary

A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.