Dual-Ring Oscillator Topology for Stable High-Speed Clock Generation
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Solution Overview
Problem
Current ring oscillators used in DRAM I/O circuits generate low-frequency clock signals that are difficult to meet high-speed requirements and are susceptible to deviations due to process, voltage, temperature, and clock load variations.
Innovation Solution
The proposed solution involves a dual-ring oscillator topology with first and second inverters connected end-to-end, where the second transmission speed is less than the first, and a frequency adjustment module to stabilize and adjust the oscillation signal, along with a buffer inverter to isolate back-end circuit impacts and maintain high multiplexing rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a current ring oscillator is used to generate clock signals in DRAM I/O circuits, then the circuit implementation is simple, but the oscillation frequency is low and difficult to meet high-speed requirements
Solution Approach 1:
The oscillator is divided into two separate ring topologies: a first ring topology with first inverters and a second ring topology with second inverters. Each ring operates independently at different speeds, allowing the system to achieve high-speed oscillation while maintaining implementation simplicity. The first ring generates high-frequency signals while the second ring provides signal conditioning and duty cycle adjustment.
2Device complexity
If a current ring oscillator is used to generate clock signals, then the circuit structure is simple, but the frequency and duty cycle are easily affected by process, voltage, temperature, and clock load variations
Solution Approach 1:
The second ring topology acts as an intermediary between the first ring oscillator and the external clock load. It receives the oscillation signal from the first ring, conditions it through its inverters, and provides a stabilized output with adjusted duty cycle. This intermediary structure isolates the core oscillation mechanism from external disturbances such as voltage variations, temperature changes, and load effects, thereby improving frequency and duty cycle stability.
3Device complexity
If a single ring topology is used for oscillation, then the circuit is simple, but it cannot simultaneously achieve high frequency and duty cycle adjustment
Solution Approach 1:
The dual-ring topology configuration enables the oscillator to perform multiple functions simultaneously. The first ring topology is optimized for high-frequency oscillation generation, while the second ring topology provides signal conditioning, duty cycle adjustment, and output buffering. This multi-functional design allows a single oscillator circuit to achieve both high frequency operation and precise duty cycle control without requiring separate circuits for each function.
Data Source
AI summary
Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.