Dual Row Lead-Frame IC Packaging for High Terminal Density
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in accommodating high-speed devices exceeding one TeraHertz, with limitations in cooling, reliability, and cost-effectiveness, while struggling to meet the demands of precision, miniaturization, and increased complexity in manufacturing.
Innovation Solution
The implementation of a dual row lead-frame system with outer and inner leads having exposed top and bottom terminals, allowing for increased terminal density without sacrificing area, which enhances input/output signal capacity and reduces parasitic inductance and resistance, enabling more robust and cost-effective packaging solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single row lead-frame is used, then the structure is simple, but the terminal density and I/O signal capacity are limited
Solution Approach 1:
The lead-frame is segmented into multiple rows (first row and second row) with separate sets of terminals, allowing independent connection to different pads on the substrate. This segmentation increases the total number of available terminals while maintaining a relatively simple overall structure that can be manufactured using standard processes.
2Quantity of substance
If terminal size is increased, then signal capacity improves, but the area occupied by terminals increases
Solution Approach 1:
The patent transitions from a single-row linear arrangement to a multi-row two-dimensional configuration. By distributing terminals across multiple rows and utilizing both top and bottom surfaces, the design achieves higher signal capacity without proportionally increasing the footprint area, as terminals are arranged in space-efficient patterns.
3Quantity of substance
If more terminals are added to increase I/O capacity, then functionality improves, but parasitic inductance and resistance increase
Solution Approach 1:
By dividing the terminal connections into multiple separate rows and paths, the current can be distributed across multiple parallel conductors. This segmentation reduces the parasitic inductance and resistance for each individual signal path, as the total impedance is reduced when multiple low-impedance paths are available in parallel.
4Area of stationary object
If package size is reduced for miniaturization, then portability improves, but cooling capability and reliability deteriorate
Solution Approach 1:
The patent utilizes a multi-row configuration that efficiently packs terminals and connection points within a compact footprint. By arranging elements in two dimensions across multiple rows rather than extending in a single direction, the design achieves miniaturization while maintaining adequate spacing for thermal management and signal integrity, thus preserving reliability in a smaller package.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.