Dual-Row Decoder Memory for In-Activation Access Count Updates
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Solution Overview
Problem
Conventional memory devices face performance degradation due to increased information decay in nearby memory cells caused by certain access patterns, necessitating optimized timing for access count update operations to prevent information loss without extending overall operation times.
Innovation Solution
The memory device employs a dual-row decoder system where access counts for word lines are stored separately, allowing access count update operations to be performed during the extended tRAS period without interfering with column commands, thus maintaining efficient operation timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If access count update operations are performed during tRAS period, then memory performance is improved and column commands can be executed without extending overall operation times, but the timing for updating access counts becomes more complex and requires separate storage locations
Solution Approach 1:
The patent divides the memory array into two separate portions: a first portion for storing data and a second portion for storing access counts. This segmentation allows access count updates to occur independently during the tRAS period without interfering with data operations, enabling parallel execution of column commands while maintaining accurate access counting for refresh operations.
Solution Approach 2:
The patent introduces a temporal dimension by performing access count updates during the tRAS period rather than after precharge. This timing shift allows the access count update operation to overlap with the data access window, enabling column commands to execute without extending the overall operation time while still completing the access count update.
2Ease of operation
If access counts are stored separately in a different portion of the memory array, then access count update operations can be performed during tRAS without interfering with column commands, but the overall device structure becomes more complex
Solution Approach 1:
The second portion of the memory array serves dual purposes: it stores access counts for refresh operations and can also function as regular data storage. This multi-functionality reduces the need for entirely separate dedicated counter circuits, integrating the access count storage within the existing memory array structure while still enabling independent update operations during tRAS.
Data Source
AI summary
A memory has a bank with at least two row decoders each of which control a respective portion of the word lines of the bank. Each word line has an associated access count which is stored along a word line in the other portion. For example, if the memory receives an activate command and a row address that specifies a first word line in the first portion, then a second word line in the second portion is also activated and an access count along the second word line is read out and updated. Since the first and second word line are activated by separate row decoders, the access count update operation may be performed during an activation time tRAS.