Dual Self-Aligned Gate Endcap Architecture for Transistor Scaling
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down multi-gate transistors due to limitations in lithographic processes, leading to trade-offs between feature size and spacing, which result in increased gate capacitance and energy consumption, and are susceptible to registration-induced shorts in self-aligned gate endcap architectures.
Innovation Solution
The implementation of dual self-aligned gate endcap (SAGE) architectures, where SAGE walls are formed both before and after a fin cut process, allowing for self-aligned gate and trench contact endcaps without the need for extra length to account for mask mis-registration, and using disposable spacers to determine endcap dimensions, thereby reducing variability and improving electrical parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lithographic processes are used to pattern semiconductor features, then the process is simpler and more established, but the spacing between features must be larger, leading to increased gate capacitance and energy consumption
Solution Approach 1:
The patent segments the gate endcap formation into two separate self-aligned processes: first SAGE walls are formed before fin cut, then additional SAGE walls are formed after fin cut. This segmentation allows each lithographic step to work at relaxed spacing while achieving tight overall spacing through the combination of both processes, thereby reducing gate capacitance and energy consumption without requiring ultra-fine single-step lithography
Solution Approach 2:
The patent introduces a temporal dimension to the SAGE wall formation process by performing it at two different stages (before and after fin cut). This multi-stage approach in the process timeline allows each stage to use conventional lithographic spacing while the cumulative effect achieves the desired tight spacing, resolving the contradiction between conventional lithography limitations and energy consumption requirements
2Manufacturing precision
If self-aligned gate endcap architectures are implemented, then manufacturing precision is improved, but the structure becomes more complex requiring multiple fabrication steps
Solution Approach 1:
The complex SAGE architecture is segmented into two manageable fabrication stages: pre-fin-cut SAGE wall formation and post-fin-cut SAGE wall formation. Each stage uses self-aligned processes that maintain high manufacturing precision while breaking down the overall complexity into two standardized, well-controlled process modules that can be integrated into existing fabrication workflows
Solution Approach 2:
The patent performs preliminary SAGE wall formation before the fin cut process, establishing a foundation structure that guides subsequent processing. This preliminary action creates reference features that enable precise alignment in the second stage, maintaining high manufacturing precision while organizing the complex multi-step process into a logical sequence of preparatory and finishing operations
Data Source
AI summary
Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.