Dual-Scale Logarithmic Counter for Accuracy-Area Tradeoffs
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Solution Overview
Problem
Counter circuits in computer systems, particularly those used in network devices, occupy significant chip area, leading to increased part costs and lower yield due to the inclusion of more transistors, while existing approximate counting algorithms introduce unacceptable inaccuracies when counting small numbers.
Innovation Solution
A dual-scale counter that divides count values into a linear range for accurate counting of small numbers and a probabilistic range for approximate counting of large numbers, using a logarithmic scale to reduce the number of bits required, thereby reducing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a linear counter is used to accurately count small numbers, then measurement precision is improved, but device complexity and chip area increase
Solution Approach 1:
The counter is divided into two separate modes: a linear counting mode for small numbers (0-15) using 4 bits, and a logarithmic counting mode for large numbers (16-65535) using 16 bits. This segmentation allows the system to use only the necessary number of bits for each counting range, reducing the average chip area required compared to using a full 16-bit linear counter for all ranges.
Solution Approach 2:
Different counting algorithms are applied to different counting ranges based on local requirements. The linear algorithm is used when high precision is needed for small numbers, while the logarithmic algorithm is used when approximate counting is acceptable for large numbers. This local quality approach optimizes the balance between accuracy and resource usage for each specific counting scenario.
2Measurement precision
If the number of bits in a counter is increased to count large numbers accurately, then measurement precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The counter dynamically switches between linear and logarithmic counting modes based on the current count value. When the count exceeds a threshold (e.g., 15), the counter transitions from linear mode to logarithmic mode, automatically adjusting its complexity to match the counting requirements. This dynamic adaptation reduces the average complexity compared to a static high-precision counter.
Solution Approach 2:
The counter changes its operational parameters (counting algorithm and bit allocation) based on the counting range. For small values, it uses linear counting with fewer bits; for large values, it uses logarithmic counting with more bits. This parameter change allows the system to optimize between precision and complexity for different operating conditions.
3Device complexity
If approximate counting algorithms are used for large numbers, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The counting range is segmented into two parts: small numbers (0-15) counted with high precision using linear algorithm, and large numbers (16-65535) counted with approximate precision using logarithmic algorithm. This segmentation ensures that approximate counting is only applied where acceptable, maintaining high precision where needed while reducing complexity where possible.
Solution Approach 2:
Different precision levels are applied locally to different counting ranges based on actual requirements. High precision linear counting is used for small numbers where accuracy is critical, while approximate logarithmic counting is used for large numbers where the relative error is acceptable. This local quality approach optimizes the trade-off between precision and complexity for each specific range.
4Ease of manufacture
If chip area is reduced to lower part costs, then manufacturing cost is improved, but the number of transistors and potential defects increase
Solution Approach 1:
The counter uses partial action by employing only the necessary number of bits for each counting range rather than always using the maximum number of bits. This reduces the average number of transistors required, lowering manufacturing cost while maintaining adequate precision for each specific counting scenario, thereby indirectly improving yield by reducing the total transistor count.
Data Source
AI summary
One aspect provides a dual-scale counter circuit that includes a counter logic unit to store a current counter value, a range-determination logic unit to determine an operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold value, and a counter-increment logic unit. The counter-increment logic unit is to increment the current counter value linearly for an increment event in response to the dual-scale counter circuit operating in a linear range and increment the current counter value probabilistically for the increment event in response to the dual-scale counter circuit operating in a probabilistic range. The dual-scale counter circuit further includes a linear-feedback shift register to generate a random binary bit sequence, based on which the counter-increment logic unit is to determine whether to increase the current counter value for the increment event when the dual-scale counter circuit operates in the probabilistic range.