Dual Scan Flip-Flop Circuit for Concurrent Normal and Test Operations
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Solution Overview
Problem
Current semiconductor integrated circuits require complete normal operation reset after each scan test, making periodic fault diagnosis inconvenient and unsuitable for applications where stopping normal operation is difficult, such as communication control systems, and leading to inefficiencies in fault diagnosis timing.
Innovation Solution
A semiconductor integrated circuit design that allows separate holding of normal and scan data using dual scan flip-flop circuits with distinct clock signals for normal and test operations, enabling concurrent execution of normal and test operations without resetting the system, and allowing distributed execution of test operations across intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan test operation is executed, then fault diagnosis capability is improved, but normal operation must be completely reset and stopped
Solution Approach 1:
The flip-flop circuit is segmented into two independent data paths: a first holding circuit for normal operation data and a second holding circuit for scan test data. This segmentation allows both normal operation and scan test to occur simultaneously without interfering with each other, resolving the contradiction between fault diagnosis capability and operation continuity.
Solution Approach 2:
The flip-flop circuit is designed with multi-functionality to serve both normal operation and scan test purposes. By incorporating dual holding circuits and selection logic, the same circuit structure can perform either normal data processing or scan test operations based on control signals, eliminating the need to stop normal operation for fault diagnosis.
2Reliability
If scan test operation is executed, then fault diagnosis is enabled, but system must be reset to initial state
Solution Approach 1:
By segmenting the data holding functionality into separate first and second holding circuits, the patent eliminates the need for system-wide reset. The scan test operation only affects the second holding circuit while the first holding circuit maintains normal operation state, thus avoiding time loss due to complete system reset.
3Productivity
If separate holding circuits are used for normal and scan data, then concurrent operation is enabled, but device complexity increases
Solution Approach 1:
The patent merges the functionality of normal operation and scan test into a single flip-flop circuit structure. By combining dual holding circuits with selection logic controlled by mode signals, the design achieves concurrent operation capability while maintaining a unified circuit architecture, thus limiting the increase in device complexity.
Solution Approach 2:
The flip-flop circuit is designed as a universal structure that can perform both normal operation and scan test functions. This multi-functionality is achieved through shared control logic and selection mechanisms, allowing the same circuit to serve multiple purposes without requiring entirely separate circuits for each function.
Data Source
AI summary
Disclosed is a semiconductor integrated circuit including a logic circuit, and a plurality of scan flip-flop circuits that hold input data or output data of the logic circuit and are capable of forming a scan chain for executing a scan test of the logic circuit. Each scan flip-flop circuit includes a scan data input part that receives input of scan data for the scan test, a normal data input part that receives input of normal data different from the scan data, and a data holding part capable of separately holding the normal data and the scan data.