Dual Scan Line Shielding for OLED RC Delay
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Solution Overview
Problem
As organic light-emitting display devices increase in size, signal line resistance and parasitic components lead to RC delays, deteriorating display quality due to increased signal transmission time.
Innovation Solution
The implementation of a dual scan line system where a thicker first scan line with lower RC delay is connected to a thinner second scan line in the non-display area, with the second scan line overlapping and shielding parasitic capacitance between the first scan line and other components, thereby reducing overall RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display device size is increased, then the display area is enlarged, but the signal line resistance and parasitic components increase causing RC delays
Solution Approach 1:
The scan line system is segmented into multiple layers (first scan line in first layer, second scan line in second layer) to distribute the signal transmission path. This segmentation allows the signal to be transmitted through multiple smaller segments rather than a single long line, reducing the overall RC delay while maintaining large display area coverage
Solution Approach 2:
The patent transitions from a single-layer scan line structure to a multi-layer structure by adding scan lines in different layers (first layer and second layer). This dimensional change allows overlapping configuration where the second scan line overlaps with the first scan line, creating parallel transmission paths that reduce signal transmission delay across large display areas
2Reliability
If the scan line thickness is increased, then the resistance is reduced, but the device complexity increases
Solution Approach 1:
Different scan lines are assigned different thicknesses based on their specific functions and positions. The first scan line has a first thickness while the second scan line has a second thickness, allowing optimization of signal transmission in critical areas without uniformly increasing complexity across the entire structure
Solution Approach 2:
The patent employs asymmetric thickness design where the first scan line and second scan line have different thicknesses. This asymmetric configuration optimizes the RC delay characteristics by providing thicker lines where needed for lower resistance while maintaining thinner lines in other areas, thereby reducing overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes signal delay and improves display quality by reducing parasitic capacitance and resistance, ensuring efficient signal transmission and maintaining high-resolution performance in large-scale organic light-emitting display devices.
Implementation Method 1
The second scan line may be disposed between the first scan line and the source and drain electrodes and may shield a parasitic capacitance between the first scan line and the source and drain electrodes
Data Source
AI summary
An organic light-emitting display device includes a substrate having a display area and a non-display area, a thin-film transistor (TFT) that includes a gate electrode and that is disposed in the display area of the substrate, a first scan line disposed in a same layer as the gate electrode that is connected to the gate electrode; and a second scan line disposed in a different layer from the first scan line that overlaps the first scan line, wherein the first scan line is connected to the second scan line in the non-display area of the substrate.