Dual Scanning Line Driving Circuit for Ghost Image Elimination
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Solution Overview
Problem
In electro-optical devices, the short scanning period leads to insufficient data signal writing, causing image display issues, and existing cross-talk prevention circuits fail to prevent simultaneous selection of adjacent scanning lines due to transistor ON current variations, resulting in longitudinal ghost images.
Innovation Solution
The electro-optical device employs a dual scanning line driving circuit structure with separate circuits for odd and even-numbered scanning lines, utilizing shift registers, calculation units, and output buffers to generate and control scanning signals, ensuring that adjacent scanning lines are not selected simultaneously by leveraging transmission delays and waveform control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the scanning period is elongated to allow sufficient data signal writing, then data signal writing is improved, but adjacent scanning lines may be selected at the same time causing longitudinal ghost images
Solution Approach 1:
The scanning line driving circuit is divided into multiple independent stages, with each stage controlling a specific scanning line. This segmentation allows precise control of each scanning line's selection timing, preventing simultaneous selection of adjacent lines while maintaining adequate scanning period for data writing.
Solution Approach 2:
The circuit performs preliminary action by ensuring that the selection signal for one scanning line is completely deactivated before the next scanning line is selected. This is achieved through the circuit design that guarantees proper timing sequence, preventing overlap in scanning line selection.
2Reliability
If a cross-talk prevention circuit using inversion delay by an inverter is provided, then prevention of simultaneous scanning line selection is improved, but variation in transistor ON current causes adjacent scanning lines to still be selected at the same time
Solution Approach 1:
The circuit incorporates feedback mechanisms that monitor the actual state of scanning line selection and adjust timing accordingly. This feedback ensures that selection signals are properly timed regardless of transistor parameter variations, making the system robust against manufacturing variations.
Solution Approach 2:
The circuit design includes timing margins and buffer stages that provide a cushion against variations in transistor characteristics. This beforehand cushioning ensures that even with manufacturing variations, adjacent scanning lines cannot be selected simultaneously.
3Reliability
If separate scanning line driving circuits are provided for odd and even-numbered scanning lines, then simultaneous selection of adjacent scanning lines is prevented, but circuit complexity increases
Solution Approach 1:
Multiple scanning line driving circuits are merged into a single integrated driving circuit block. This merging reduces overall circuit complexity while maintaining the functional separation needed to prevent simultaneous selection of adjacent scanning lines.
Solution Approach 2:
The scanning line driving circuit is designed with universal stages that can control multiple scanning lines. Each stage is multi-functional, capable of driving different scanning lines at different times, which reduces the total number of circuit elements needed.
Data Source
AI summary
An electra-optical device includes an electra-optical panel having scanning lines, data lines, and pixels corresponding to intersections of the scanning lines and the data lines. First and second scanning line driving circuits output scanning signals to odd-numbered scanning lines and even-numbered scanning lines, respectively. A pixel forming region is located between the first and second scanning line driving circuits. Each of the first and second scanning line driving circuits includes a shift register unit, an output control circuit, and an output buffer unit. The shift register unit sequentially shifts a start pulse based on a clock signal to produce output signals. The output control circuit generates scanning signals based on logical products of the scanning signals from the other of the first and second scanning line driving circuits and the output signals. The output buffer unit outputs the scanning signals to the scanning lines.