Dual Semiconductor Film CMP Planarization
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Solution Overview
Problem
Chemical mechanical polishing (CMP) in semiconductor manufacturing often results in dishing in low pattern density regions, leading to over-polishing and open circuits due to poor surface planarity of semiconductor devices.
Innovation Solution
Depositing two semiconductor films with different CMP removal rates before the CMP process, where a first semiconductor film with a higher removal rate is used to expose a stop layer, and a second film with a lower removal rate fills trenches to prevent dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is performed on semiconductor device, then surface planarity is improved, but dishing occurs in low pattern density regions causing open circuits
Solution Approach 1:
The patent applies local quality by depositing a first semiconductor film specifically in low pattern density regions (trenches) where dishing is prone to occur, while leaving high pattern density regions unchanged. This localized approach allows differential CMP removal rates that prevent dishing in vulnerable areas without affecting other regions, thereby resolving the contradiction between achieving surface planarity and preventing open circuits.
Solution Approach 2:
The patent implements preliminary action by depositing the first semiconductor film with different CMP removal rate characteristics before performing the CMP process. This preparatory step modifies the surface topology in advance, creating a structure that compensates for anticipated dishing during CMP, thus preventing the harmful effect while maintaining the beneficial planarization.
2Manufacturing precision
If additional oxide-reduction etching step is performed prior to CMP, then polishing time is reduced to prevent dishing, but process complexity increases
Solution Approach 1:
The patent changes the material composition parameter by depositing a first semiconductor film with specific properties (different CMP removal rate) in low pattern density regions. This parameter change in film composition allows the CMP process itself to achieve dishing prevention without requiring additional etching steps, thereby resolving the contradiction between dishing prevention and process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves surface planarity by preventing trench dishing during CMP, thereby reducing the risk of open circuits from metal interconnect collapse or breaks.
Implementation Method 1
A chemical-mechanical polishing (CMP) process is performed until the stop layer is exposed
Implementation Method 2
A first semiconductor film is deposited conformally on the stop layer and the trench
Data Source
AI summary
A method for planarizing a semiconductor device includes steps herein. A substrate is provided, on which a stop layer is formed. A trench is formed in the substrate. A first semiconductor film is deposited conformally on the stop layer and the trench. A second semiconductor film is deposited to fill the trench and cover the first semiconductor film. A chemical-mechanical polishing process is performed until the stop layer is exposed. A removal rate of the chemical-mechanical polishing process on the first semiconductor film is higher than that on the second semiconductor film. The first dielectric layer on the substrate selectively is removed.