Dual Semiconductor Memory Write Cache for Storage Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data storage devices face inefficiencies in head positioning and data storage due to limited endurance of semiconductor memory, leading to increased access latency and reduced throughput, particularly with large write commands and fragmented blocks.
Innovation Solution
Implementing a dual semiconductor memory system with a first SM for small write commands and a second SM with lower endurance for large write commands, utilizing a write cache to store data based on thresholds, and dynamically adjusting cache size and usage based on queue depth and write transfer rate to extend memory life and improve throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single semiconductor memory is used for write caching, then the device complexity is low, but the throughput is limited and access latency increases for large write commands
Solution Approach 1:
The write cache is divided into two separate semiconductor memories: a first SM for small write commands and a second SM for large write commands. This segmentation allows each memory to be optimized for its specific workload, improving overall throughput without requiring a single oversized memory system.
Solution Approach 2:
The patent introduces a new dimension of classification by separating write commands based on size thresholds. Small writes go to the first SM while large writes go to the second SM, creating a dimensional split in the write cache architecture that improves performance for both command types simultaneously.
2Reliability
If semiconductor memory endurance is increased, then the memory life is extended, but the cost and device complexity increase
Solution Approach 1:
Different semiconductor memories are selected with different endurance characteristics based on their specific usage requirements. The first SM handles small writes with higher frequency, while the second SM handles large writes with lower frequency, allowing each component to have locally optimized quality matching its workload.
Solution Approach 2:
The patent employs a second semiconductor memory with lower endurance (potentially less expensive) for large write commands, accepting that it will have a shorter operational life but compensating through wear leveling techniques and the fact that large writes are less frequent than small writes.
3Loss of time
If write cache size is increased to reduce access latency, then the throughput improves, but the garbage collection operations increase and memory life decreases
Solution Approach 1:
By segmenting the write cache into two separate semiconductor memories, the patent reduces the garbage collection burden on each individual memory. The first SM handles small writes with more frequent garbage collection, while the second SM handles large writes with less frequent garbage collection, extending overall system reliability.
Solution Approach 2:
The patent changes the parameter of cache organization from a single unified memory to a segmented dual-memory system, which fundamentally alters the garbage collection behavior and extends memory life by distributing wear across two separate memory components with different endurance characteristics.
4Productivity
If a dual semiconductor memory system is implemented, then the throughput for large write commands improves, but the device complexity and initial cost increase
Solution Approach 1:
The write cache is segmented into two semiconductor memories with different endurance characteristics, allowing the system to handle both small and large write commands efficiently. This segmentation improves throughput by matching memory types to workload characteristics.
Solution Approach 2:
Each semiconductor memory is selected with specific local quality characteristics (endurance, speed, capacity) matched to its intended workload. The first SM is optimized for small writes while the second SM is optimized for large writes, creating a heterogeneous memory system with locally optimized performance.
Data Source
AI summary
A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.