Dual Sense Node Charge Sharing for QLC Memory Sensing
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Solution Overview
Problem
As NAND Flash memory transitions from triple-level cells (TLC) to quad-level cells (QLC) and beyond, the increased sensitivity to sensing time leads to higher fail bit counts due to tighter sense margins, necessitating improved sensing circuitry for accurate data storage and retrieval.
Innovation Solution
The implementation of sensing circuitry that involves pre-charging and charge-sharing between two sense nodes to enhance the sense margin, providing better noise immunity and more accurate sensing results, particularly in QLC configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensing circuitry uses traditional single sense node configuration, then device complexity is low, but measurement precision deteriorates due to tighter sense margins in QLC configurations
Solution Approach 1:
The sensing circuitry is segmented into two separate sense nodes (first sense node and second sense node) instead of using a single sense node. Each sense node independently senses the state of the memory cell, and their combined output provides enhanced measurement precision and improved sense margin for QLC configurations.
2Reliability
If sensing circuitry uses traditional configuration, then ease of operation is maintained, but reliability deteriorates due to higher fail bit counts from tighter sense margins
Solution Approach 1:
The sensing function is divided into two separate sense nodes that independently evaluate memory cell states. This segmentation provides redundant sensing paths, reducing fail bit counts and improving reliability by ensuring that a single node failure or error does not compromise the entire sensing operation.
Solution Approach 2:
The sensing circuitry incorporates feedback mechanisms where the outputs from both sense nodes are combined and evaluated. The circuitry uses feedback to adjust sensing thresholds and margins dynamically, improving reliability by compensating for variations and reducing fail bit counts in QLC configurations.
3Productivity
If memory system uses QLC configuration, then productivity increases due to higher storage capacity, but measurement precision deteriorates due to increased sensitivity to sensing time
Solution Approach 1:
The dual sense node configuration segments the sensing task to handle the increased complexity of QLC configurations. Each sense node can be optimized for specific voltage thresholds, enabling accurate differentiation of the four storage states while maintaining productivity benefits of QLC.
Solution Approach 2:
The sensing circuitry dynamically adjusts parameters such as voltage thresholds and sensing timing based on the detected state. This parameter adaptation allows the system to maintain high measurement precision across all four QLC states (00, 01, 10, 11) while preserving the high storage capacity productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in performance gains of 0.2 MB/s to 0.8 MB/s and improved noise immunity, making the memory systems less sensitive to bit-line settling time and variations in threshold voltages.
Implementation Method 1
memory cell sensing by charge sharing between two sense nodes
Data Source
AI summary
Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.