Dual-Server Storage Controller Data Difference Checking
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Solution Overview
Problem
In dual-server storage controllers, existing methods for checking data differences in synchronous writes are inefficient, leading to prolonged error detection and hardening times, which can result in delayed recovery from failures and increased I/O latency.
Innovation Solution
A method and system that utilize a summary longitudinal redundancy check (LRC) code to compare data across nodes, allowing for faster error detection and earlier hardening of tracks by computing error detecting codes for each record and comparing them to ensure data integrity, with bit-by-bit comparison as a fallback for missed errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bit-by-bit comparison is performed between first node and second node for error detection, then measurement precision is improved, but time consumption increases significantly
Solution Approach 1:
The patent divides the data track into multiple records, and computes error detecting codes (LRC) for each record separately. This segmentation allows parallel processing of error detection across different records, significantly reducing the total time required compared to bit-by-bit comparison of the entire track, while maintaining accurate error detection capability.
Solution Approach 2:
The patent introduces error detecting codes (LRC - Longitudinal Redundancy Check) as an intermediary mechanism to verify data consistency between first node and second node. Instead of directly comparing all bits, the LRC codes serve as compact representatives that can be computed and compared quickly, achieving accurate error detection with minimal time overhead.
2Reliability
If comprehensive data verification is performed before track hardening, then reliability is improved, but I/O latency increases
Solution Approach 1:
The patent performs error detecting code computation during the data writing process itself, rather than as a separate verification step after writing completes. By computing LRC codes for each record as data is written to both first node and second node, the verification is preliminary and integrated, ensuring data integrity without adding post-write latency that would delay track hardening.
3Productivity
If error detecting codes are computed for each record during writing, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent transforms the error detection problem from bit-level operations to record-level LRC code computations. By changing the parameter of verification from individual bits to aggregated LRC codes for each record, the computational complexity is reduced while maintaining detection accuracy, enabling faster error detection that improves overall productivity.
Data Source
AI summary
A storage controller receives a plurality of synchronous writes from a host via a bus interface, wherein each of the synchronous writes is received for writing to a first node and a second node of the storage controller. For each record of a track written to the first node and the second node, an error detecting code is computed on writing the record. In response to determining that computed error detecting codes do not match for any corresponding records of the track in the first node and the second node, an indication of an error is transmitted from the storage controller to the host.