Dual Shift Register Data Serializer Circuit
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Solution Overview
Problem
Existing data serialization methods face challenges in achieving high-speed data throughput due to difficulties in balancing delays between multiple signal paths, leading to data pulse position errors and complex implementation in modern circuit topologies.
Innovation Solution
A data serializer circuit utilizing two N-bit shift registers operating 180 degrees out of phase with clock frequencies related to the input clock by a factor of N/2, combined with a 2:1 multiplexer and driver, to generate a high-speed serial data stream, simplifying the implementation by alternating selection between the shift registers and eliminating the need for balanced delay paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple signal paths are used for high-speed data serialization, then data throughput increases, but delay balancing becomes complex and errors occur
Solution Approach 1:
The invention divides the parallel data into two separate N-bit data streams (first and second N-bit data) that are processed through separate shift registers. This segmentation allows each path to be independently controlled and timed, eliminating the need for complex delay balancing across multiple paths while maintaining high data throughput.
Solution Approach 2:
The invention uses periodic clock signals with specific phase relationships (180 degrees out of phase) to control the shift registers alternately. This periodic action with defined timing ensures that data from both paths is serialized in a systematic sequence without requiring complex delay balancing, achieving high throughput through structured periodic operation.
2Speed
If clock frequency is increased to achieve high-speed serialization, then data rate improves, but setup and hold time requirements become harder to meet
Solution Approach 1:
The invention employs periodic clock signals with a frequency relationship where the output clock is M times the reference clock frequency. The shift registers are controlled by these periodic clocks with defined phase relationships, ensuring that data is captured and shifted at predictable intervals that satisfy setup and hold time requirements even at high speeds.
Solution Approach 2:
The data aligner performs preliminary alignment of the input data streams before they enter the shift registers. This preliminary action ensures that data is properly positioned and ready for capture at the correct clock edges, meeting setup and hold time requirements before the high-speed serialization begins.
3Ease of manufacture
If simple serialization methods are used, then implementation is easier, but data pulse position errors occur
Solution Approach 1:
The invention segments the data into two separate N-bit streams processed by separate shift registers with defined timing relationships. This segmentation provides a simple yet precise structure where each register handles a specific portion of the data with controlled timing, achieving both ease of implementation and accurate pulse positioning through the systematic alternation of the two streams.
Data Source
AI summary
A data serializer includes a data aligner, two N-bit shift registers, a 2-1 multiplexer, and a driver, wherein N is the number of parallel input data bits. Data is received and aligned by the data aligner, which is arranged to drive odd and even data lines to a respective one of the N-bit shift registers. One N-bit shift register is arranged to operate with a clock that is 180 degrees out of phase with respect to the other N-bit shift register. The frequency of the clock for each N-bit shift register is related to an input clock frequency by a factor of N/2. The multiplexer is arranged to alternate the selection of the N-bit shift registers to provide the output signal. The output of the multiplexer corresponds to a high-speed serial data stream that can be provided to a driver such as LVDS, DVI, PPDS or RSDS drivers.